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A.K. Kumaran

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Doctoral thesis (2026) - A.K. Kumaran, S.M. Alavi, L.C.N. de Vreede
The ever-increasing demand for data transmission, driven by the need to support global economic growth, is being addressed by fifth-generation (5G) networks. 5G offers several advantages over previous cellular generations, including low network latency, enhanced link robustness, improved mobility, energy efficiency, and superior spectral efficiency. These advancements are expected to have a transformative impact on industries worldwide by creating new job opportunities and boosting productivity. To achieve multi-Gbit/s data transmission and low-latency line-of-sight links, 5G systems utilize the millimeter-wave (mm-wave) spectrum and advanced modulation schemes such as quadrature amplitude modulation (QAM). The mm-wave spectrum supports large modulation bandwidths that enable higher data rates but suffer from increased signal attenuation. Similarly, spectrally efficient higher-order modulation schemes like QAM improve data rates but require higher signal-to-noise ratio (SNR). By combining mm-wave spectrum usage with complex modulation schemes and phased arrays, 5G networks achieve high-speed, low-latency performance. However, this also imposes stringent requirements on output power (Pout), error vector magnitude (EVM), and adjacent channel leakage ratio (ACLR). Additionally, orthogonal frequency-division multiplexing (OFDM) is used in 5G for its high spectral efficiency, immunity to frequency selective fading, and power efficiency. However, it introduces high peak-to-average power ratio (PAPR) that necessitate efficiency at both peak power and power back-off (PBO) in transmitters (TXs).

Chapter 2 examines the fundamental performance metrics in power amplifier (PA) design, which serves as a critical bottleneck in mm-wave 5G systems. It reviews various PA classes, explores challenges associated with mm-wave operation, and discusses existing solutions. The chapter also introduces design equations for a 2-way Doherty PA and evaluates its operation and performance. While N-way Doherty PAs show promise for achieving required power levels and improving average efficiency in complementary metal-oxide-semiconductor (CMOS) technology, they face limitations such as narrow bandwidth, low gain, nonlinearity, and sensitivity to voltage standingwave ratio (VSWR). These challenges make mm-wave N-way Doherty PAs an active area of research.

Chapter 3 presents a systematic design process for 3-/4-/5-way Doherty networks using transmission lines (TLs) and lumped elements, which can also be extended to N-way configurations. These power combiners are designed and compared using both lossless and lossy components with a quality factor (QF) of 15/25 for inductors/capacitors at 30 GHz, while their PAs are modeled as ideal current sources. Based on this analysis, it reveals that the 3-way network is themost efficient and practical candidate for mm-wave frequencies, requiring fewer components and offering comparable performance to the 4-way configuration.

Chapter 4 introduces a single-supply balun-first 3-way parallel Doherty PA designed for mm-wave 5G applications. This design incorporates a bandwidth enhancement technique to broaden the operational frequency range, improve broadband PBO efficiency, and reduce impedance mismatches. Realized in 40 nm CMOS bulk technology with a core area of 0.77mm2, the prototype achieves a Psat/peak gain of over 20 dBm/16 dB and demonstrates a drain efficiency (DE) of 15 %/22 %/33% at 9.5 dB/6 dB /0 dB PBO across a 24–30GHz band. It supports 64-QAM OFDM signals with an EVM/ACLR of −24.3 dB/−30.1 dBc at 9.4dBm average output power (Pavg) and achieves promising results with 1024-QAM signals. However, the 3-way Doherty PAs show efficiency limitations compared to 2-way Doherty PAs at 9.5 dB PBO due to finite QF of the drain-source capacitance (Cds), device channel resistance, and higher passive losses of the output network.

Chapter 5 describes a 4×2-way Doherty PA designed for mm-wave 5G applications. Featuring an advanced output combiner with four differential 2-way Doherty networks, two quadrature hybrid couplers (QHCs), and a balun, this design enhances Pout and PBO efficiency. Realized in 40 nm CMOS bulk technology with a core area of 1.54mm2, the prototype achieves a Psat/peak gain of 25.2dBm/25.5 dB and a DE of 17.5 %/10% at 0 dB/6 dB PBO across a 26–32GHz band. It delivers exceptional EVM/ACLR performance for both 64-QAM and 1024-QAM OFDM signals and demonstrates resilience to VSWR variations. By incorporating artificial intelligence digital pre-distortion (AI-DPD), the PA achieves a Pavg of 15.3dBm for 400MHz 64-QAM signals, making it a strong candidate for 5G mm-wave TXs or phased arrays.

Chapter 6 summarizes the findings of the thesis, compares them with the state-of-the-art, and highlights key conclusions. It also suggests future research directions, such as a novel floor plan for the TX chain. This includes the use of four 2-way series Doherty PAs to achieve high output power and improved PBO efficiency. Additionally, flip-chip integration is proposed to position antenna connection pads centrally, reducing interconnect parasitics and unwanted losses. ...
This article introduces a 4 x 2 -way Doherty power amplifier (PA) tailored for millimeter-wave (mm-wave) 5G applications. It incorporates an advanced output combiner that consists of four differential 2-way Doherty networks, two quadrature hybrid couplers (QHCs), and a balun to enhance the output power Pout and improves power back-off (PBO) efficiency. Realized in 40 nm CMOS bulk technology with a core area of 1.54 mm2, the prototype delivers a saturated power/peak gain surpassing 25.2 dBm/25.5 dB, and it demonstrates a drain efficiency (DE) exceeding 17.5%/10% at 0 dB/6 dB PBO across a 26–32 GHz band. The proposed mm-wave PA achieves error vector magnitude (EVM)/adjacent channel leakage ratio (ACLR) values of −25 dB/−33 dBc for a 2 GHz 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal with 9.6 dB PAPR, operating at an average output power (Pavg) of 11.3 dBm with an average drain efficiency (DEavg) of 4% without using digital predistortion (DPD). For a 50 MHz 1024-QAM OFDM signal with 10 dB PAPR, it achieves a Pavg/DEavg of 7.2 dBm/2% with EVM/ACLR of −35 dB/−42 dBc without DPD. ...

This article introduces a single-supply balun-first three-way parallel Doherty power amplifier (PA) tailored for millimeter-wave (mm-wave) fifth-generation (5G) applications. It incorporates a bandwidth enhancement technique that widens the operational frequency range, enhances broadband power back-off (PBO) efficiency, and reduces impedance mismatch between differential PAs. Realized in 40-nm CMOS bulk technology with a core area of 0.77 mm2 , the prototype delivers a saturated power/peak gain surpassing 20 dBm/16 dB, and it demonstrates a drain efficiency (DE) exceeding 15%/22%/33% at 9.5 dB/6 dB/0 dB PBO across a 24–30 GHz band. The proposed mm-wave PA achieves EVM/ACLR values of − 24.3 dB/ − 30.1 dBc for a 1-GHz 64-QAM OFDM signal, operating at an average output power (Pout) of 9.4 dBm with an average DE of 15%. For a 50-MHz 1024-QAM OFDM signal, it achieves an average Pout/DE of 8.6 dBm/12% with EVM/ACLR of − 30 dB/ − 36.3 dBc. ...
This article introduces an N-way chain-weaver balanced power amplifier (PA) for millimeter-wave (mm-wave) phased-array transmitters (TXs). Taking advantage of the proposed combining network, an embedded impedance/power sensor is implemented, which can be utilized for output power regulation, built-in self-test, and load-based performance optimization. The proposed PA architecture offers linearity and gain robustness under the antenna's frequency/time-dependent voltage standing wave ratio (VSWR). In the event of impedance mismatch, the proposed PA provides N different loads equally distributed on the VSWR circle. Consequently, the performance of the PAs is the average of N PAs with N different loads, which makes this structure VSWR resilient. As a proof of concept, an eight-way chain-weaver balanced PA (BPA) is realized in 40-nm bulk CMOS technology, and it delivers 25.19-dBm P SAT with 16.19% PAE. The proposed PA supports a 2-GHz 64-QAM OFDM signal with 16-dBm average power, achieving -25-dB error vector magnitude (EVM). The average EVM is better than -30.3 dB without digital pre-distortion (DPD) for an "800-MHz 256-QAM OFDM"signal while generating an average output power of 12.17 dBm. The performance of the PA is also evaluated under 1.5:1-3:1 VSWR conditions. The measured small-signal gain variation under VSWR 3:1 is ±0.7 dB. Moreover, assuming any frequency/time-dependent loading condition within the VSWR 3:1 circle, the proposed chain-weaver BPA achieves <2.8° amplitude-to-phase (AM-PM) over 3-GHz bandwidth. Besides, the embedded impedance/power sensor accuracy outperforms the state of the art. The proposed impedance sensor can measure VSWR 3:1 by the maximum angle and magnitude errors of 12.3° and 0.106, respectively. ...
Conference paper (2023) - Anil Kumar Kumaran, Masoud Pashaeifar, Hossein Mashad Nemati, Leo C.N. De Vreede, Morteza S. Alavi
This paper presents a 40nm CMOS mm-wave 3-way Doherty power amplifier (PA) suitable for 5G mm-wave transmitters. It features a bandwidth-enhanced technique using a compact single-supply balun-first 3-way Doherty combiner. The realized front-end with a core area of 0.77 mm2delivers a peak power/gain of more than 20 dBm/16 dB and a drain efficiency (DE) of better than 15 %/22 %/33 % at 9.5 dB/6 dB/0 dB power back-off across a 24-to-30 GHz band. At 26 GHz, it achieves an EVM/ACLR of -23.5 dB/-29.5 dBc for an 800MHz 64-OFDM signal with 9.8 dBm average output power and a 15 % average DE. ...
Conference paper (2022) - Anil Kumaran, Hossein Mashad Nemati, Leo C.N. de Vreede, Morteza S. Alavi
This paper presents a design procedure for compact lumped-element 3-/4-/5-way Doherty power combiners suitable for mm-wave 5G transmitters. Among them, the 3-way Doherty power combiner is favored due to its low complexity, compact layout, and average drain efficiency at 12 dB power back-off (PBO) when implemented using lossy lumped elements. Based on the metal stack of a 40nm CMOS process, a 3-way Doherty power combiner can provide a simulated passive efficiency of more than 60% at 12 dB PBO and a 10% drain-efficiency bandwidth $(BW_{\mathrm{D}\mathrm{E}10\%})/3\mathrm{d}\mathrm{B}$ power bandwidth $(BW_{3\mathrm{d}\mathrm{B}})$ of 8/15 GHz at 30 GHz. ...
Line-of-sight millimeter-wave (mm-wave) 5G phased array systems are key solutions to overcome the free-space path loss while providing a multi-Gbit/s data throughput. To realize these systems, nanoscale CMOS technologies should be exploited to enable high integration, compact area, low cost, and high yield. Besides, 5G systems typically employ spectrally efficient complex modulation schemes with high peak-to-average power ratios (PAPRs), which demand the transmitter (TX) power amplifier (PA) to operate in power back-off (PBO), thus degrading its average efficiency. Many techniques such as outphasing [1,2], load-modulated balanced amplifiers (LMBAs) [3–4], and Doherty PAs (DPAs) [5–9] are adopted in mm-wave TXs to enhance efficiency at PBO. Among them, the Doherty is an “RF-in RF-out” PBO efficiency enhancement topology supporting signals with large modulation bandwidth. These mm-wave DPAs are inherently narrowband structures due to employing a lumped-element quarter-wave transmission line (QTL). Thus, the broadband operation is only feasible by increasing the complexity of the Doherty power combiner, compromising with its passive efficiency [7–8]. Also, in these architectures, their optimum PAE at PBO is still narrowband while providing broadband P1dB. ...
Conference paper (2021) - Anil Kumar Kumaran, Masoud Pashaeifar, Marco D'Avino, Leo C.N. de Vreede, Morteza S. Alavi
Continuous Class F (CCF) power amplifiers (PAs) overcome Class-F PA's disadvantage of narrow bandwidth by relaxing the short-circuit requirement at the 2nd harmonic while still maintaining 90.7% peak efficiency over the band of interest. This paper proposes four different CCF output networks, with their design procedure, suitable for on-chip implementation in the 2.1-2.7GHz band. The output stage with 2nd harmonic trap and no RF choke is favoured due to its flat real impedance, low fundamental reactance, and compact layout. Using a 40nm CMOS process, a passive efficiency of 68% at 2.4GHz for this structure is in reach. ...