The degradation mechanisms of silicon carbide (SiC) VDMOSFET and trench metal oxide semiconductor field effect transistor (MOSFET) in a 60Co gamma irradiation environment were investigated. The degradation of electrical characteristics of SiC MOSFET in different working states after irradiation with different total ionizing doses (TIDs) was explored. The defects induced during the irradiation process were studied in annealing experiments conducted after irradiation. The reasons for the degradation of SiC MOSFET caused by TID were revealed, and a prediction model of threshold voltage (Vth) shift was proposed and verified through TCAD simulation. The Vth, breakdown voltage (BV), on-resistance R, input capacitance (Ciss), output capacitance Coss, and reverse transfer capacitance C _rss were measured at different irradiation doses and annealing conditions. Experimental results indicated that the degradation of both Ron and Ciss was primarily caused by the Vth shift. As the doses increased, the shift in Vth gradually reached saturation. Similar trends to VDMOSFET were observed in trench MOSFET but with greater sensitivity to TID. In addition, MOSFETs biased at zero voltage exhibited lower shifts in Vth compared with those under high gate bias conditions. Furthermore, the increase in defects in the gate oxide during irradiation and annealing processes were calculated. Finally, a model predicting Vth shift path was established, and its accuracy and limitations were determined. This study provides valuable insights into the effect of TID on SiC MOSFETs.

This work employed the particle swarm optimization (PSO) algorithm to assess the trade-off between breakdown voltage (BV) and on-state resistance (R DS,on ) in 4H–SiC metal oxide semiconductor field effect transistors (MOSFET) for power devices. In this work, the numerical model obtained after analyzing the resistance composition is utilized as the objective function in PSO to determine characteristic parameters in double-diffused metal oxide semiconductor field effect transistors (DMOSFET). These equations are input for the PSO algorithm. The derived characteristic parameters include the drift region doping concentration and thickness, cell size, channel length, JFET region length, JFET region thickness, and doping concentration. To adhere to common application constraints, this work optimizes these characteristic parameters to minimize the R DS,on under typical BV ranging from 100 to 2000 V. The R DS,on for some typical applications was extracted and validated through TCAD simulations to ensure algorithm accuracy. The reported results confirm that PSO yields superior outcomes and may be considered when designing devices. This work offers helpful insights into the design of characteristic parameters for 4H–SiC power DMOSFET devices and evaluates the feasibility of using PSO to optimize the characteristic parameters of power devices.

Nano-metal materials have received considerable attention because of their promising performance in wide bandgap semiconductor packaging. In this study, molecular dynamics (MD) simulation was performed to simulate the nano-Cu sintering mechanism and the subsequent mechanical behaviors. Hybrid sintering, comprising nanosphere (NS) and nanoflake (NF), was performed at temperatures from 500 to 650 K. Furthermore, shear and tensile simulations were conducted with constant strain rates on the sintered structure at multiple temperatures. Subsequently, the extracted mechanical properties were correlated with the sintering behavior. The results revealed that the mechanical properties of the nano-Cu sintered structure could be improved by tuning material composition and increasing the sintering temperature. We established a relationship between the sintered microstructure and mechanical response. The shear modulus and shear strength of the sintered structure with NF particles increased to 41.20 and 3.51 GPa respectively. Furthermore, the elastic modulus increased to 55.60, and the tensile strength increased to 4.88 GPa. This result provides insights into the preparation phase of nano-Cu paste for sintering technology.

In the domain of power electronics, especially for applications requiring high power, high temperature, and high frequency, Silicon Carbide Metal Oxide Semiconductor Field-Effect Transistors (SiC MOSFETs) stand out due to their excellent properties such as high thermal conductivity, elevated breakdown electric field, and minimal power loss. These devices are pivotal in the reliability and safety of electric vehicles, where avalanche-induced failures represent a significant risk within automotive uses. This study extensively explores the avalanche ruggedness of both planar and trench SiC MOSFET configurations through a combination of Unclamped Inductive Switching (UIS) testing in single and multiple pulse scenarios, and Technology Computer-Aided Design (TCAD) simulations. Initial UIS experiments revealed the primary failure mechanisms and their origins in SiC MOSFETs. Following empirical analysis, TCAD simulations were employed to develop comprehensive models of these devices., enhancing the understanding of failure dynamics during UIS conditions. The integration of empirical and simulation data supports the creation of advanced strategies to reduce the risk of avalanche failures, thereby enhancing the durability and reliability of Wide Bandgap Semiconductor devices.