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Guo, J. (author)
This thesis presents a Delay Locked Loop(DLL) based Single Slope ADC. Compared to the convertional Single Slope ADC, the readout speed is increased by 16 times. A DLL is designed with a start-controlled Phase Frequency Detector (PFD), a differential ended Charge Pump (CP) and fully differential Delay Cells (DC). The multi-stage comparator with...
master thesis 2011
Xu, Y. (author)
This thesis presents a CMOS image sensor which can implement the charge domain interlacing principle. Inspired by the shared amplifier pixel structure and based on a pinned photodiode four transistor (4T) structure, two innovative pixel designs combined with two different readout directions are presented. These novel pixels are designed to fit...
master thesis 2009