This article presents a BJT-based temperature-to-digital-converter (TDC) that achieves ±0.25 °C 3 sigma -inaccuracy from -40 °C to +180 °C after a heater-assisted voltage calibration (HA-VCAL). Its switched-capacitor (SC) ADC employs two sampling capacitors and, thus, the minimum number of critical sampling switches, which minimizes the effects of switch leakage at high temperatures and improves accuracy. The TDC is also equipped with an on-chip heater, with which the sensing BJTs can be rapidly (<0.5 s) heated to about 110 °C. This, in turn, enables VCAL at two different temperatures without the need for a temperature-controlled environment. Realized in a 0.16- mu text {m} standard CMOS, the TDC, including the on-chip heater, occupies 0.15 mm² and operates from 1.8 V.

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This paper presents an area- and energy-efficient sensor readout circuit, which can precisely digitize temperature, capacitance and voltage. The three modes use only on-chip references and employ a shared zoom ADC based on SAR and ΔΣ conversion to save die area. Measurements on 24 samples from a single wafer show a temperature inaccuracy of ±0.2 °C (3σ) over the military temperature range (-55°C to 125°C). The voltage sensing shows an inaccuracy of ±0.5%. The sensor also offers 18.7-ENOB capacitance-to-digital conversion, which handles up to 3.8 pF capacitance with a 0.76 pJ/conv.-step energy-efficiency FoM. It occupies 0.33 mm in a 0.16 μm CMOS process and draws 4.6 μA current from a 1.8 V supply.@en

This paper presents a BJT-based temperature sensor, which can be accurately trimmed in both ceramic and plastic packages, on the basis of purely electrical measurements at room temperature. This is achieved by combining the voltage-calibration technique from [1] with an on-chip heater, which can heat the sensing BJTs from room temperature to ∼85°C in 0.5s. Measurements show that the sensor can then be trimmed to an inaccuracy of ±0.3°C (3σ) over the military range (-55 to +125°C). This is similar to the inaccuracy obtained after conventional temperature calibration, i.e., at well-defined temperatures, but requires much less calibration time and infrastructure.

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This paper presents a precision CMOS temperature-to-digital converter (TDC), which senses the temperature-dependent base-emitter voltage of substrate PNPs. Measurements on 20 samples from one batch show that it achieves an inaccuracy of ±60 mK (3σ) from-55 °C to +125 °C, after a single room-temperature trim. This state-of-the-art result is mainly due to the extensive use of dynamic error cancellation techniques to generate the PNP's collector currents, thus minimizing the spread in their base-emitter voltages, together with a digital PTAT trim to correct for the spread in the PNP's saturation currents. The effect of process variation on the TDC's inaccuracy was investigated by measuring 80 samples from three different batches. Using the same calibration parameters, they exhibit a maximum untrimmed inaccuracy of ±2 °C (3σ) from-55 °C to +125 °C. This drops to ±100 mK (3σ) after a single point trim. The proposed TDC thus reduces calibration costs by obviating the need for batch-specific calibration parameters, which would otherwise require the multipoint calibration of several samples. The effect of the PNP's current gain β was also investigated with the help of a novel β-detection circuit. Implemented in 0.16-μm CMOS, the TDC occupies 0.16 mm² and draws 4.6 μA from 1.5 to 2 V supply voltages. It achieves a resolution Figure of Merit of 7.8 pJ°C², and a state-of-the-art supply sensitivity of 0.01 °C/V.

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This paper presents the most accurate BJT-based CMOS temperature-to-digital converter (TDC) ever reported, with an inaccuracy of ±60mK (3σ) from -70°C to 125°C. This is 2× better than the state-of-the-art, despite being implemented in a process (160nm) that only offers low-βF (<;5) PNPs. It is also the most energy-efficient ever reported, with a resolution FOM of 7.3pJ°C2. This level of performance is achieved by an improved βF-compensation scheme, the use of dynamic error correction techniques to suppress non-BJT related errors and the use of an energy-efficient zoom-ADC based on current-reuse OTAs. These techniques also result in very low power-supply sensitivity (12mK/V), thus maintaining TDC accuracy for supply voltages ranging from 1.5V to 2V.@en