This article describes a high-performance capacitance-to-digital converter (CDC) for sub-nm displacement sensing with an electrically floating target. Intended to be integrated into a displacement sensor probe, the CDC consumes only 560μW. It achieves 98.5-dB SNR in a 1-ms conversion time. With a sensing O 8-mm probe and a 25μm stand-off distance from the target, it achieves 0.18-nm resolution. Moreover, it offers an in-band common-mode rejection ratio (CMRR) higher than 117 dB, providing decent electric field interference immunity.

This paper describes a high-performance Capacitance-to-Digital Converter (CDC) for sub-nm displacement sensing with an electrically floating target. Intended to be integrated into a displacement sensor probe, the CDC consumes only 560μW. It achieves 98.5dB SNR in a 1ms conversion time, which is 34 times more energy-efficient than the prior art. Moreover, it also offers a 117dB in-band (1kHz) Common-mode Rejection Ratio (CMRR), providing decent electric field interference immunity.

This paper describes a high-resolution energy-efficient CMOS temperature sensor, intended for the temperature compensation of MEMS/quartz frequency references. The sensor is based on silicided poly-silicon thermistors, which are embedded in a Wien-bridge RC filter. When driven at a fixed frequency, the filter exhibits a temperature-dependent phase shift, which is digitized by an energy-efficient continuous-time phase-domain delta-sigma modulator. Implemented in a 0.18-μm CMOS technology, the sensor draws 87 μA from a 1.8 V supply and achieves a resolution of 410 μKrms in a 5-ms conversion time. This translates into a state-of-the-art resolution figure-of-merit of 0.13 pJ·K². When packaged in ceramic, the sensor achieves an inaccuracy of 0.2 °C (3σ) from -40 °C to 85 °C after a single-point calibration and a correction for systematic nonlinearity. This can be reduced to ±0.03 °C (3σ) after a first-order fit. In addition, the sensor exhibits low 1/f noise and packaging shift.

This paper presents a precision CMOS temperature-to-digital converter (TDC), which senses the temperature-dependent base-emitter voltage of substrate PNPs. Measurements on 20 samples from one batch show that it achieves an inaccuracy of ±60 mK (3σ) from-55 °C to +125 °C, after a single room-temperature trim. This state-of-the-art result is mainly due to the extensive use of dynamic error cancellation techniques to generate the PNP's collector currents, thus minimizing the spread in their base-emitter voltages, together with a digital PTAT trim to correct for the spread in the PNP's saturation currents. The effect of process variation on the TDC's inaccuracy was investigated by measuring 80 samples from three different batches. Using the same calibration parameters, they exhibit a maximum untrimmed inaccuracy of ±2 °C (3σ) from-55 °C to +125 °C. This drops to ±100 mK (3σ) after a single point trim. The proposed TDC thus reduces calibration costs by obviating the need for batch-specific calibration parameters, which would otherwise require the multipoint calibration of several samples. The effect of the PNP's current gain β was also investigated with the help of a novel β-detection circuit. Implemented in 0.16-μm CMOS, the TDC occupies 0.16 mm² and draws 4.6 μA from 1.5 to 2 V supply voltages. It achieves a resolution Figure of Merit of 7.8 pJ°C², and a state-of-the-art supply sensitivity of 0.01 °C/V.

This paper presents an integrated shunt-based current-sensing system (CSS) capable of handling ±36-A currents, the highest ever reported. It also achieves a 0.3% gain error and a 400-μA offset, which is significantly better than the state-of-the-art systems. The heart of the system is a robust 260-μ Ω shunt resistor made from the lead frame of a standard HVQFN plastic package. The resulting voltage drop is then digitized by a precision Δ Σ ADC and a bandgap reference (BGR). At the expense of current handling capability, a ±5-A version of the CSS uses a 10-mΩ on-chip metal shunt to achieve just a 4-μ A offset. Both designs are realized in a standard 0.13-μm CMOS process and draw 13 μA from a 1.5-V supply. Compensation of the spread and nonlinear temperature dependency of the shunt resistor R_shunt is accomplished by the use of a fixed polynomial master curve and a single room temperature calibration. This procedure also effectively compensates for the residual spread and nonlinearity of the ADC and the BGR.