Computing-in-Memory (CIM) architectures using memristive crossbar arrays enable energy-efficient AI acceleration. Analog non-idealities, such as IR drop and nonlinearity, impose design constraints that existing simulators cannot capture and thus explore effectively. Current approaches sacrifice either modeling accuracy or simulation speed, preventing systematic design space exploration. In this paper we propose X-Sim, a crossbar simulator that resolves this trade-off through a modular architecture. Our approach decouples device physics from circuit analysis using a fixed-point scheme, avoiding expensive Jacobian computations while preserving device fidelity. X-Sim delivers SPICE-level accuracy (< 1% error) with up to 200× speedup over physics-based simulators. This enables quick and systematic design space exploration across thousands of configurations, guiding reliable system design. X-Sim will be released as open source.

Although offering great potential for energy-efficient edge-AI, memristor-based CIM accelerators are severely hindered by IR drop induced errors. To tackle this, we propose a low-cost mitigation technique by first quantifying the impact of IR drop on the accuracy. Then, a mitigation strategy is developed to compensate for IR drop-induced inference accuracy reduction by combining an optimized mapping scheme with a fine-tuned calibration of the ADC. Results show the proposed solution can effectively mitigate IR drop with a negligible overhead.

Neuromorphic computing offers a promising solution for realizing energy-efficient and compact Artificial Intelligence (AI) systems. Implemented with Spiking Neural Networks (SNNs), neuromorphic systems can benefit from SNN characteristics, such as event-driven computation, event sparsity, biological plausibility, etc., to achieve high performance and energy efficiency, an aspect vital for the realization of AI at the edge. Although SNNs are biology-inspired structures, their use in mission- and safety-critical applications raises multiple concerns around the trustworthiness of neuromorphic hardware due to various intrinsic and extrinsic reliability and security issues. Hence, adequately studying the dependability of SNNs and neuromorphic hardware accelerators becomes of utmost importance, in order to expose and harden against potential vulnerabilities, so that a reliable and secure operation is ensured. This paper presents an analysis of the dependability and trustworthiness aspects of SNNs and neuromorphic hardware. It outlines potential mitigation and countermeasure strategies to improve the reliability, testability, and security aspects of SNN hardware and ensure its trustworthy deployment in critical application domains.

Advancements in Artificial Intelligence (AI) and Internet-of-Things (IoT) have increased demand for edge AI, but deployment on traditional AI accelerators, like GPUs and TPUs, using von Neumann architecture, suffer from inefficiencies due to separate memory and compute units. Computation-in-Memory (CIM), utilizing non-volatile memristor devices to leverage analog computing principles and perform in-place computations, holds great potential in improving computational efficiency by eliminating frequent data movement. However, standard implementation of CIM faces several challenges, primarily high power consumption and subsequently induced nonlinearity, debating its viability for edge devices. In this paper, we propose C3CIM, a novel memristor-based CIM micro-architecture, featuring a new bit-cell and array design, targeting efficient implementation of Neural Networks (NN). Our architecture uses a constant current source to perform Multiply-and-Accumulate (MAC) operations with a very low computation current (10 to 100 nA), thereby significantly enhancing power efficiency. We adapted C3CIM for Spiking Neural Networks (SNN) and developed a prototype using TSMC 40nm CMOS node for on-silicon validation. Furthermore, our micro-architecture was benchmarked using two SNN models based on N-MNIST and IBM-Gesture datasets, for comparison against current state-of-the-art (SOTA). Results show up to 35x reduction in power along with 6.7x saving in energy compared to SOTA, demonstrating promising potential of this work for edge AI applications.

Real-time edge artificial intelligence (AI) demands memory elements that are not only energy-efficient and multifunctional, but also compact, tunable, and integrable with flexible substrates. Planar memory architecture offers distinct advantages for neuromorphic computing, including surface accessibility, facile fabrication, and seamless integration with flexible substrates, making it ideal for next-generation synaptic hardware. Traditional metal oxide-based memristors often fail to meet all these requirements simultaneously due to their rigid architecture and limited material versatility. Herein, we present a planar Ti³C²T^x-MXene-based memristor (PMX-memristor) fabricated on a flexible cyclic olefin copolymer (COC) substrate, constituting the first fully planar MXene-based resistive device reported to date. The planar architecture exposes the active MXene channel, which enables direct surface inspection and functionalization while delivering robust analog switching. By tuning the voltage amplitude, the device operates in two modes: (i) a volatile regime based on valence change dynamics with transient conductance states, and (ii) a non-volatile regime driven by voltage-induced Ti→TiOx transformation, supporting eight distinct resistance levels. Detailed EDX and XPS analyses, performed before and after electrical stress, confirm the voltage-induced oxidation pathway that underpins this dual-mode behavior. The memristor’s eight-level precision enables compact 9-bit weight encoding using 3×3-bit multi-level cells in crossbar arrays, reducing area and energy compared to binary implementations. We demonstrate end-to-end deployment of these devices in spiking neural networks for real-time classification of neuromorphic vision datasets, showcasing high-performance, task-relevant learning capabilities on benchmarks such as N-MNIST and DVS-Gesture. These results underscore the potential of the designed PMX-memristor for voltage-controlled, neuromorphic edge computing and provide direct surface accessibility for functionalization and potential bio-interfacing for next-generation smart wearables.