T. Spyrou
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The hardware demand to accelerate neural network inference in the context of machine learning (ML) and artificial intelligence (AI) has been rapidly growing. Complex models and the widespread use of AI in various domains have led to the problem of energy budget for AI in datacenters becoming a critical problem. The primary contributor is the frequent data movement between memory and processing units, requiring new computing paradigms supporting fast yet energy-efficient neural network inference. Computing-in-Memory (CIM) addresses the “memory wall” of von Neumann architectures by performing parallel computations directly in the memory array. Various memory technologies, including emerging non-volatile memories (NVMs) such as RRAM, FeRAM, PCRAM, STT-MRAM, and optimised structures of conventional SRAM, have been explored for CIM applications.
Designing CIM systems requires multi-level simulation approaches because device or circuit-level design choices can significantly impact system-level efficiency and accuracy. Simulations for CIM architectures span a broad spectrum, from high-level analytical models that provide quick but coarse estimates to detailed circuit-level simulations that provide accuracy at the cost of scalability. However, this leaves a gap in evaluating CIM architectures at realistic workload scales while maintaining sufficient fidelity. This work targets the intermediate cycle- and system-level domain to address this, aiming to bridge the gap between abstract analytical evaluations and low-level hardware description implementations.
This work develops an event-based CIM architecture simulation framework showcased by the simulation of an accelerator system defined with a target multiply and accumulate (MAC) block architecture. Workloads, including basic MLP, CNN, and NLP models, were executed to analyse metrics such as cycle delay, tile count and utilisation as an efficiency indicator. The impact of tunable simulation parameters was also evaluated considering four defined MAC block topologies. Simulation results show for an MLP workload an increase of 7.6% tile utilisation between two topologies, while reporting on both the number of execution cycles and necessary hardware.
Overall, the CIM architecture simulation platform can effectively serve as a tool for mid-stage design exploration and performance evaluation of CIM-based accelerators. The framework’s modular, eventbased structure enables architectural exploration while providing realistic timing behaviour, distinguishing it from analytical and device-level tools. ...
Designing CIM systems requires multi-level simulation approaches because device or circuit-level design choices can significantly impact system-level efficiency and accuracy. Simulations for CIM architectures span a broad spectrum, from high-level analytical models that provide quick but coarse estimates to detailed circuit-level simulations that provide accuracy at the cost of scalability. However, this leaves a gap in evaluating CIM architectures at realistic workload scales while maintaining sufficient fidelity. This work targets the intermediate cycle- and system-level domain to address this, aiming to bridge the gap between abstract analytical evaluations and low-level hardware description implementations.
This work develops an event-based CIM architecture simulation framework showcased by the simulation of an accelerator system defined with a target multiply and accumulate (MAC) block architecture. Workloads, including basic MLP, CNN, and NLP models, were executed to analyse metrics such as cycle delay, tile count and utilisation as an efficiency indicator. The impact of tunable simulation parameters was also evaluated considering four defined MAC block topologies. Simulation results show for an MLP workload an increase of 7.6% tile utilisation between two topologies, while reporting on both the number of execution cycles and necessary hardware.
Overall, the CIM architecture simulation platform can effectively serve as a tool for mid-stage design exploration and performance evaluation of CIM-based accelerators. The framework’s modular, eventbased structure enables architectural exploration while providing realistic timing behaviour, distinguishing it from analytical and device-level tools. ...
The hardware demand to accelerate neural network inference in the context of machine learning (ML) and artificial intelligence (AI) has been rapidly growing. Complex models and the widespread use of AI in various domains have led to the problem of energy budget for AI in datacenters becoming a critical problem. The primary contributor is the frequent data movement between memory and processing units, requiring new computing paradigms supporting fast yet energy-efficient neural network inference. Computing-in-Memory (CIM) addresses the “memory wall” of von Neumann architectures by performing parallel computations directly in the memory array. Various memory technologies, including emerging non-volatile memories (NVMs) such as RRAM, FeRAM, PCRAM, STT-MRAM, and optimised structures of conventional SRAM, have been explored for CIM applications.
Designing CIM systems requires multi-level simulation approaches because device or circuit-level design choices can significantly impact system-level efficiency and accuracy. Simulations for CIM architectures span a broad spectrum, from high-level analytical models that provide quick but coarse estimates to detailed circuit-level simulations that provide accuracy at the cost of scalability. However, this leaves a gap in evaluating CIM architectures at realistic workload scales while maintaining sufficient fidelity. This work targets the intermediate cycle- and system-level domain to address this, aiming to bridge the gap between abstract analytical evaluations and low-level hardware description implementations.
This work develops an event-based CIM architecture simulation framework showcased by the simulation of an accelerator system defined with a target multiply and accumulate (MAC) block architecture. Workloads, including basic MLP, CNN, and NLP models, were executed to analyse metrics such as cycle delay, tile count and utilisation as an efficiency indicator. The impact of tunable simulation parameters was also evaluated considering four defined MAC block topologies. Simulation results show for an MLP workload an increase of 7.6% tile utilisation between two topologies, while reporting on both the number of execution cycles and necessary hardware.
Overall, the CIM architecture simulation platform can effectively serve as a tool for mid-stage design exploration and performance evaluation of CIM-based accelerators. The framework’s modular, eventbased structure enables architectural exploration while providing realistic timing behaviour, distinguishing it from analytical and device-level tools.
Designing CIM systems requires multi-level simulation approaches because device or circuit-level design choices can significantly impact system-level efficiency and accuracy. Simulations for CIM architectures span a broad spectrum, from high-level analytical models that provide quick but coarse estimates to detailed circuit-level simulations that provide accuracy at the cost of scalability. However, this leaves a gap in evaluating CIM architectures at realistic workload scales while maintaining sufficient fidelity. This work targets the intermediate cycle- and system-level domain to address this, aiming to bridge the gap between abstract analytical evaluations and low-level hardware description implementations.
This work develops an event-based CIM architecture simulation framework showcased by the simulation of an accelerator system defined with a target multiply and accumulate (MAC) block architecture. Workloads, including basic MLP, CNN, and NLP models, were executed to analyse metrics such as cycle delay, tile count and utilisation as an efficiency indicator. The impact of tunable simulation parameters was also evaluated considering four defined MAC block topologies. Simulation results show for an MLP workload an increase of 7.6% tile utilisation between two topologies, while reporting on both the number of execution cycles and necessary hardware.
Overall, the CIM architecture simulation platform can effectively serve as a tool for mid-stage design exploration and performance evaluation of CIM-based accelerators. The framework’s modular, eventbased structure enables architectural exploration while providing realistic timing behaviour, distinguishing it from analytical and device-level tools.
Precise and Fast Simulation of RRAM Crossbar Arrays
The design and implementation of a fast simulation framework for resistive memristor-based computation in memory crossbar arrays
This thesis presents a RRAM-crossbar simulation framework aimed at precise and fast simulation.
Specifically, the model simulates a memristive crossbar with parasitic wire resistances, generating output currents and tracking the internal memristive states based on applied input voltages. Implemented in C++, the developed model has a clear interface making it suitable for integration into larger simulation frameworks for CIM-based accelerators. Experimental results demonstrate that the simulator is significantly faster than Cadence Spectre, while maintaining sufficient accuracy for use in behavioral-level CIM simulations.
The complete model is divided into three sub-modules: a memristor model, a linear crossbar model, and a non-linear crossbar model. The memristor model is based on the JART VCM v1b var model by Bengel et al. [2], and its implementation is a faithful translation of the associated Verilog-A code [3], with additional functionality for simulation in C++. Additionally, other memristor models can be implemented through an abstract memristor class.
Experimental results show that the developed simulation framework is significantly faster than Cadence Spectre while retaining a relative error below 1%. Additionally, the crossbar and the memristors are modeled to more closely reflect physical device behaviour than in other RRAM simulation frameworks. Finally, a study of linear and non-linear memristor simulation in a crossbar shows a measurable difference, suggesting approximating memristors as linear impacts simulation accuracy ...
Specifically, the model simulates a memristive crossbar with parasitic wire resistances, generating output currents and tracking the internal memristive states based on applied input voltages. Implemented in C++, the developed model has a clear interface making it suitable for integration into larger simulation frameworks for CIM-based accelerators. Experimental results demonstrate that the simulator is significantly faster than Cadence Spectre, while maintaining sufficient accuracy for use in behavioral-level CIM simulations.
The complete model is divided into three sub-modules: a memristor model, a linear crossbar model, and a non-linear crossbar model. The memristor model is based on the JART VCM v1b var model by Bengel et al. [2], and its implementation is a faithful translation of the associated Verilog-A code [3], with additional functionality for simulation in C++. Additionally, other memristor models can be implemented through an abstract memristor class.
Experimental results show that the developed simulation framework is significantly faster than Cadence Spectre while retaining a relative error below 1%. Additionally, the crossbar and the memristors are modeled to more closely reflect physical device behaviour than in other RRAM simulation frameworks. Finally, a study of linear and non-linear memristor simulation in a crossbar shows a measurable difference, suggesting approximating memristors as linear impacts simulation accuracy ...
This thesis presents a RRAM-crossbar simulation framework aimed at precise and fast simulation.
Specifically, the model simulates a memristive crossbar with parasitic wire resistances, generating output currents and tracking the internal memristive states based on applied input voltages. Implemented in C++, the developed model has a clear interface making it suitable for integration into larger simulation frameworks for CIM-based accelerators. Experimental results demonstrate that the simulator is significantly faster than Cadence Spectre, while maintaining sufficient accuracy for use in behavioral-level CIM simulations.
The complete model is divided into three sub-modules: a memristor model, a linear crossbar model, and a non-linear crossbar model. The memristor model is based on the JART VCM v1b var model by Bengel et al. [2], and its implementation is a faithful translation of the associated Verilog-A code [3], with additional functionality for simulation in C++. Additionally, other memristor models can be implemented through an abstract memristor class.
Experimental results show that the developed simulation framework is significantly faster than Cadence Spectre while retaining a relative error below 1%. Additionally, the crossbar and the memristors are modeled to more closely reflect physical device behaviour than in other RRAM simulation frameworks. Finally, a study of linear and non-linear memristor simulation in a crossbar shows a measurable difference, suggesting approximating memristors as linear impacts simulation accuracy
Specifically, the model simulates a memristive crossbar with parasitic wire resistances, generating output currents and tracking the internal memristive states based on applied input voltages. Implemented in C++, the developed model has a clear interface making it suitable for integration into larger simulation frameworks for CIM-based accelerators. Experimental results demonstrate that the simulator is significantly faster than Cadence Spectre, while maintaining sufficient accuracy for use in behavioral-level CIM simulations.
The complete model is divided into three sub-modules: a memristor model, a linear crossbar model, and a non-linear crossbar model. The memristor model is based on the JART VCM v1b var model by Bengel et al. [2], and its implementation is a faithful translation of the associated Verilog-A code [3], with additional functionality for simulation in C++. Additionally, other memristor models can be implemented through an abstract memristor class.
Experimental results show that the developed simulation framework is significantly faster than Cadence Spectre while retaining a relative error below 1%. Additionally, the crossbar and the memristors are modeled to more closely reflect physical device behaviour than in other RRAM simulation frameworks. Finally, a study of linear and non-linear memristor simulation in a crossbar shows a measurable difference, suggesting approximating memristors as linear impacts simulation accuracy
Master thesis
(2025)
-
L.E. Hoogland, S. Hamdioui, A.B. Gebregiorgis, Theofilos Spyrou, D.G. Muratore, A.N.N. Mahmoud
Modern Artificial Intelligence (AI) applications, such as Deep Neural Networks (DNNs), require substantial amounts of data in order to carry out the classification or recognition task, which must be retrieved from the memory, supplied to the processor, and finally the results stored back in the memory. In Von-Neumann architectures, this data movement incurs significant performance costs, leaving the CPU with many idle cycles while waiting for data to arrive. One way of addressing this issue is by investigating alternative computing paradigms, such as Computation in Memory (CIM). In CIM architectures, the processor and the memory are integrated into one physical location. As such, computations are performed in the memory core directly, without the need to be transferred to a central processor. A promising technology to efficiently implement CIM crossbar arrays is the emerging Ferroelectric Field Effect Transistor (FeFET), in which data can be stored in a non-volatile manner in the polarization state of a ferroelectric layer.
In existing literature, CIM crossbar arrays are optimized for the inference task, but do not perform the learning task locally. This means the neural network is trained externally, for example using cloud computing. Only once the training is finished, the weights are written to the physical crossbar array. For medical applications, such as ECG classification, sending sensitive medical data off to the cloud for training leads to privacy concerns. A solution to this problem is On-chip learning: training the network locally in the crossbar itself.
This thesis focuses on integrating the FeFET technology in a CIM architecture to design a crossbar array that supports On-Chip learning for Convolutional Neural Networks. The accelerator overcomes the memory-wall inherent to Von Neumann machines by embracing the CIM framework and uses FeFET devices to overcome the scaling walls associated with CMOS technology. The result is a novel accelerator which leverages the parallelism of Analog Crossbars to optimize the inference task and forward propagation, while leveraging the accuracy of Digital Crossbars to optimize the back propagation task. ...
In existing literature, CIM crossbar arrays are optimized for the inference task, but do not perform the learning task locally. This means the neural network is trained externally, for example using cloud computing. Only once the training is finished, the weights are written to the physical crossbar array. For medical applications, such as ECG classification, sending sensitive medical data off to the cloud for training leads to privacy concerns. A solution to this problem is On-chip learning: training the network locally in the crossbar itself.
This thesis focuses on integrating the FeFET technology in a CIM architecture to design a crossbar array that supports On-Chip learning for Convolutional Neural Networks. The accelerator overcomes the memory-wall inherent to Von Neumann machines by embracing the CIM framework and uses FeFET devices to overcome the scaling walls associated with CMOS technology. The result is a novel accelerator which leverages the parallelism of Analog Crossbars to optimize the inference task and forward propagation, while leveraging the accuracy of Digital Crossbars to optimize the back propagation task. ...
Modern Artificial Intelligence (AI) applications, such as Deep Neural Networks (DNNs), require substantial amounts of data in order to carry out the classification or recognition task, which must be retrieved from the memory, supplied to the processor, and finally the results stored back in the memory. In Von-Neumann architectures, this data movement incurs significant performance costs, leaving the CPU with many idle cycles while waiting for data to arrive. One way of addressing this issue is by investigating alternative computing paradigms, such as Computation in Memory (CIM). In CIM architectures, the processor and the memory are integrated into one physical location. As such, computations are performed in the memory core directly, without the need to be transferred to a central processor. A promising technology to efficiently implement CIM crossbar arrays is the emerging Ferroelectric Field Effect Transistor (FeFET), in which data can be stored in a non-volatile manner in the polarization state of a ferroelectric layer.
In existing literature, CIM crossbar arrays are optimized for the inference task, but do not perform the learning task locally. This means the neural network is trained externally, for example using cloud computing. Only once the training is finished, the weights are written to the physical crossbar array. For medical applications, such as ECG classification, sending sensitive medical data off to the cloud for training leads to privacy concerns. A solution to this problem is On-chip learning: training the network locally in the crossbar itself.
This thesis focuses on integrating the FeFET technology in a CIM architecture to design a crossbar array that supports On-Chip learning for Convolutional Neural Networks. The accelerator overcomes the memory-wall inherent to Von Neumann machines by embracing the CIM framework and uses FeFET devices to overcome the scaling walls associated with CMOS technology. The result is a novel accelerator which leverages the parallelism of Analog Crossbars to optimize the inference task and forward propagation, while leveraging the accuracy of Digital Crossbars to optimize the back propagation task.
In existing literature, CIM crossbar arrays are optimized for the inference task, but do not perform the learning task locally. This means the neural network is trained externally, for example using cloud computing. Only once the training is finished, the weights are written to the physical crossbar array. For medical applications, such as ECG classification, sending sensitive medical data off to the cloud for training leads to privacy concerns. A solution to this problem is On-chip learning: training the network locally in the crossbar itself.
This thesis focuses on integrating the FeFET technology in a CIM architecture to design a crossbar array that supports On-Chip learning for Convolutional Neural Networks. The accelerator overcomes the memory-wall inherent to Von Neumann machines by embracing the CIM framework and uses FeFET devices to overcome the scaling walls associated with CMOS technology. The result is a novel accelerator which leverages the parallelism of Analog Crossbars to optimize the inference task and forward propagation, while leveraging the accuracy of Digital Crossbars to optimize the back propagation task.
To address the “memory wall” of von Neumann architectures, computation-in-memory (CIM) emerges as a promising paradigm that performs computation directly within memory, thereby enhancing energy efficiency and performance by minimizing data movement. This thesis explores a CIM tile architecture for 1T1R memristor crossbar arrays, supporting fundamental operations including write, read, verification, logic (AND, OR, XOR), and vector-matrix multiplication (VMM). The proposed design integrates key components including input/output buffers, analog interfaces such as Digital-to-Input Modules, Sample&Hold modules, and Analog-to-Digital Converters (ADCs), as well as a comprehensive digital periphery. The digital periphery encompasses the Column Selection, Row Selection, Row Data Selection, and Spare Row Selection modules, Logical Unit, Verification Unit, Read Register, and threestage Addition Unit dedicated to VMM.
A significant part of our work is the RTL design and gate-level implementation of the tile’s comprehensive digital periphery. As part of this effort, we design and implement a novel Verification Unit that performs offline validation of data written to the crossbar array. This unit detects write errors, initiates selective rewriting of faulty cells, and performs re-verification. If a failure persists, it automatically flags the affected row, disables it for future computations, and triggers remapping to a spare row. Furthermore, we develop analytical models for estimating the area and energy consumption of the digital periphery, based on the characterized gate-level implementation.
The remapping functionality is validated through RTL simulation and the gate-level implementation of the tile’s comprehensive digital periphery is evaluated through post-synthesis simulations using Cadence Genus. We analyze area and energy consumption across key architectural parameters including crossbar size, number of ADCs, operand width, number of spare rows, external bus width, and WDS/RDS instruction data field width. Area analysis shows linear growth with crossbar size and spare rows, non-monotonic relationship with operand width (first decreasing then increasing), increasing trend with ADC count, and inverse relationships with bus width and data field width. Energy analysis reveals that store operations exhibit quadratic scaling with crossbar size and inverse proportionality with bus width;verification, read, and logic operations show quadratic scaling with crossbar size and inverse relationships with ADC count; VMM operations display linear scaling with crossbar size, inverse relationship with ADC count, and inverse proportionality with WDS/RDS instruction data field width. These findings provide valuable guidance for parameter optimization in CIM tile design. ...
A significant part of our work is the RTL design and gate-level implementation of the tile’s comprehensive digital periphery. As part of this effort, we design and implement a novel Verification Unit that performs offline validation of data written to the crossbar array. This unit detects write errors, initiates selective rewriting of faulty cells, and performs re-verification. If a failure persists, it automatically flags the affected row, disables it for future computations, and triggers remapping to a spare row. Furthermore, we develop analytical models for estimating the area and energy consumption of the digital periphery, based on the characterized gate-level implementation.
The remapping functionality is validated through RTL simulation and the gate-level implementation of the tile’s comprehensive digital periphery is evaluated through post-synthesis simulations using Cadence Genus. We analyze area and energy consumption across key architectural parameters including crossbar size, number of ADCs, operand width, number of spare rows, external bus width, and WDS/RDS instruction data field width. Area analysis shows linear growth with crossbar size and spare rows, non-monotonic relationship with operand width (first decreasing then increasing), increasing trend with ADC count, and inverse relationships with bus width and data field width. Energy analysis reveals that store operations exhibit quadratic scaling with crossbar size and inverse proportionality with bus width;verification, read, and logic operations show quadratic scaling with crossbar size and inverse relationships with ADC count; VMM operations display linear scaling with crossbar size, inverse relationship with ADC count, and inverse proportionality with WDS/RDS instruction data field width. These findings provide valuable guidance for parameter optimization in CIM tile design. ...
To address the “memory wall” of von Neumann architectures, computation-in-memory (CIM) emerges as a promising paradigm that performs computation directly within memory, thereby enhancing energy efficiency and performance by minimizing data movement. This thesis explores a CIM tile architecture for 1T1R memristor crossbar arrays, supporting fundamental operations including write, read, verification, logic (AND, OR, XOR), and vector-matrix multiplication (VMM). The proposed design integrates key components including input/output buffers, analog interfaces such as Digital-to-Input Modules, Sample&Hold modules, and Analog-to-Digital Converters (ADCs), as well as a comprehensive digital periphery. The digital periphery encompasses the Column Selection, Row Selection, Row Data Selection, and Spare Row Selection modules, Logical Unit, Verification Unit, Read Register, and threestage Addition Unit dedicated to VMM.
A significant part of our work is the RTL design and gate-level implementation of the tile’s comprehensive digital periphery. As part of this effort, we design and implement a novel Verification Unit that performs offline validation of data written to the crossbar array. This unit detects write errors, initiates selective rewriting of faulty cells, and performs re-verification. If a failure persists, it automatically flags the affected row, disables it for future computations, and triggers remapping to a spare row. Furthermore, we develop analytical models for estimating the area and energy consumption of the digital periphery, based on the characterized gate-level implementation.
The remapping functionality is validated through RTL simulation and the gate-level implementation of the tile’s comprehensive digital periphery is evaluated through post-synthesis simulations using Cadence Genus. We analyze area and energy consumption across key architectural parameters including crossbar size, number of ADCs, operand width, number of spare rows, external bus width, and WDS/RDS instruction data field width. Area analysis shows linear growth with crossbar size and spare rows, non-monotonic relationship with operand width (first decreasing then increasing), increasing trend with ADC count, and inverse relationships with bus width and data field width. Energy analysis reveals that store operations exhibit quadratic scaling with crossbar size and inverse proportionality with bus width;verification, read, and logic operations show quadratic scaling with crossbar size and inverse relationships with ADC count; VMM operations display linear scaling with crossbar size, inverse relationship with ADC count, and inverse proportionality with WDS/RDS instruction data field width. These findings provide valuable guidance for parameter optimization in CIM tile design.
A significant part of our work is the RTL design and gate-level implementation of the tile’s comprehensive digital periphery. As part of this effort, we design and implement a novel Verification Unit that performs offline validation of data written to the crossbar array. This unit detects write errors, initiates selective rewriting of faulty cells, and performs re-verification. If a failure persists, it automatically flags the affected row, disables it for future computations, and triggers remapping to a spare row. Furthermore, we develop analytical models for estimating the area and energy consumption of the digital periphery, based on the characterized gate-level implementation.
The remapping functionality is validated through RTL simulation and the gate-level implementation of the tile’s comprehensive digital periphery is evaluated through post-synthesis simulations using Cadence Genus. We analyze area and energy consumption across key architectural parameters including crossbar size, number of ADCs, operand width, number of spare rows, external bus width, and WDS/RDS instruction data field width. Area analysis shows linear growth with crossbar size and spare rows, non-monotonic relationship with operand width (first decreasing then increasing), increasing trend with ADC count, and inverse relationships with bus width and data field width. Energy analysis reveals that store operations exhibit quadratic scaling with crossbar size and inverse proportionality with bus width;verification, read, and logic operations show quadratic scaling with crossbar size and inverse relationships with ADC count; VMM operations display linear scaling with crossbar size, inverse relationship with ADC count, and inverse proportionality with WDS/RDS instruction data field width. These findings provide valuable guidance for parameter optimization in CIM tile design.
Memristor-based Computation-In-Memory (CIM) architectures are a genre of emerging computing designs, and they have the potential to provide a power-efficient computational power for artificial intelligence (AI). However, current memristor-based CIM designs face the challenges from non-idealities, such as read disturb. The mitigation of non-idealities in CIM architectures is an area of active research.
Simulation tools are important design tools for CIM. Conventionally, SPICE simulations are used for CIM architectures. Modern high-level simulation frameworks for CIM are faster when compared to SPICE, and therefore it is desirable to investigate the feasibility of non-ideality analysis, such as read disturb analysis, in high-level simulations. However, current high-level simulators do not include a model for read disturb, and they are not suitable for read disturb analysis.
To fill this gap, this thesis presents RdaCIM, a read-disturb-aware CIM simulator. RdaCIM is high-level simulation tool that exploits parallelism provided by multi-core CPUs and AVX instructions. More importantly, RdaCIM involves the non-trivial non-ideality of read disturb into the simulations, which makes it possible for the user to perform read disturb related investigations on the simulator.
Experiments have been done with RdaCIM to show the feasibility of read disturb analysis on this tool. The effectiveness of a rewriting scheme as a countermeasure to read disturb is verified on RdaCIM. Furthermore, an effort to reduce the overhead of rewriting by dynamic voltage adjustment is presented and verified with RdaCIM. Performance benchmarks have been done to elaborate the benefits of the parallelised implementation of the simulation tool. ...
Simulation tools are important design tools for CIM. Conventionally, SPICE simulations are used for CIM architectures. Modern high-level simulation frameworks for CIM are faster when compared to SPICE, and therefore it is desirable to investigate the feasibility of non-ideality analysis, such as read disturb analysis, in high-level simulations. However, current high-level simulators do not include a model for read disturb, and they are not suitable for read disturb analysis.
To fill this gap, this thesis presents RdaCIM, a read-disturb-aware CIM simulator. RdaCIM is high-level simulation tool that exploits parallelism provided by multi-core CPUs and AVX instructions. More importantly, RdaCIM involves the non-trivial non-ideality of read disturb into the simulations, which makes it possible for the user to perform read disturb related investigations on the simulator.
Experiments have been done with RdaCIM to show the feasibility of read disturb analysis on this tool. The effectiveness of a rewriting scheme as a countermeasure to read disturb is verified on RdaCIM. Furthermore, an effort to reduce the overhead of rewriting by dynamic voltage adjustment is presented and verified with RdaCIM. Performance benchmarks have been done to elaborate the benefits of the parallelised implementation of the simulation tool. ...
Memristor-based Computation-In-Memory (CIM) architectures are a genre of emerging computing designs, and they have the potential to provide a power-efficient computational power for artificial intelligence (AI). However, current memristor-based CIM designs face the challenges from non-idealities, such as read disturb. The mitigation of non-idealities in CIM architectures is an area of active research.
Simulation tools are important design tools for CIM. Conventionally, SPICE simulations are used for CIM architectures. Modern high-level simulation frameworks for CIM are faster when compared to SPICE, and therefore it is desirable to investigate the feasibility of non-ideality analysis, such as read disturb analysis, in high-level simulations. However, current high-level simulators do not include a model for read disturb, and they are not suitable for read disturb analysis.
To fill this gap, this thesis presents RdaCIM, a read-disturb-aware CIM simulator. RdaCIM is high-level simulation tool that exploits parallelism provided by multi-core CPUs and AVX instructions. More importantly, RdaCIM involves the non-trivial non-ideality of read disturb into the simulations, which makes it possible for the user to perform read disturb related investigations on the simulator.
Experiments have been done with RdaCIM to show the feasibility of read disturb analysis on this tool. The effectiveness of a rewriting scheme as a countermeasure to read disturb is verified on RdaCIM. Furthermore, an effort to reduce the overhead of rewriting by dynamic voltage adjustment is presented and verified with RdaCIM. Performance benchmarks have been done to elaborate the benefits of the parallelised implementation of the simulation tool.
Simulation tools are important design tools for CIM. Conventionally, SPICE simulations are used for CIM architectures. Modern high-level simulation frameworks for CIM are faster when compared to SPICE, and therefore it is desirable to investigate the feasibility of non-ideality analysis, such as read disturb analysis, in high-level simulations. However, current high-level simulators do not include a model for read disturb, and they are not suitable for read disturb analysis.
To fill this gap, this thesis presents RdaCIM, a read-disturb-aware CIM simulator. RdaCIM is high-level simulation tool that exploits parallelism provided by multi-core CPUs and AVX instructions. More importantly, RdaCIM involves the non-trivial non-ideality of read disturb into the simulations, which makes it possible for the user to perform read disturb related investigations on the simulator.
Experiments have been done with RdaCIM to show the feasibility of read disturb analysis on this tool. The effectiveness of a rewriting scheme as a countermeasure to read disturb is verified on RdaCIM. Furthermore, an effort to reduce the overhead of rewriting by dynamic voltage adjustment is presented and verified with RdaCIM. Performance benchmarks have been done to elaborate the benefits of the parallelised implementation of the simulation tool.