This paper provides a comprehensive analysis of the DC and RF behavior of HBTs, spanning temperatures from 350 to 3.8 K. It underscores the necessity of detailed studies for the design of RF circuits for quantum computing, including LNAs, VCOs, and mixers, due to the absence of cryogenic models. The DC gain shows betas of 800 at room temperature (RT) and 3000 at 3.8 K. RF characterization indicates a maximum fT of 500 GHz at 3.8 K and 300 GHz at RT. The proposed figure-of-merit, (gm.fT/Ic), typically used in CMOS design, is explored across the temperature range. The study reveals a noise equivalent temperature of sub-1 K at 3.8 K with source matching. The noise behavior of Si/SiGe:C HBTs within 0.13 μ m BiCMOS technology is characterized over 293 to 4 K and 10 kHz to 12 GHz. The analysis shows a significant increase in the flicker noise coefficient, K, and corner frequency reduction at 4 K. The high frequency parameter fT reaches 500 GHz, demonstrating better performance compared to advanced CMOS nodes. This research supports the modeling of HBTs that are critical for circuits operating at cryogenic temperatures. These models are particularly beneficial for designing classical-to-quantum interfaces.

Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is studied, towards an all-operating-region mismatch model. An overall increase of variability is shown, in particular in the subthreshold region at cryogenic temperatures due to a dramatic increase of the subthreshold slope mismatch. Mismatch in strong inversion is modeled by the Croon model while the weak-inversion region is modeled by taking subthresh-old slope variability into account. This results in the first model capable of predicting mismatch over the whole range of operating regions and temperatures.

A multipurpose monolithic array of 2 × 2 multichannel digital silicon photomultipliers (MD-SiPMs) fabricated in 40-nm CMOS technology is presented. Each MD-SiPM comprises 64 × 64 smart pixels connected to 128 low-power 45-ps sliding-scale time-to-digital converters (TDCs). The system can operate in two different modes: 1) event-driven and 2) frame-based. The first is suited for positron emission tomography (PET) and the second for synchronous applications like LiDAR. The design includes electronics to capture gamma events by means of a scintillator. The digital readout is fully embedded in the sensor and it is reconfigurable by SPI. Data packets are sent following a simple protocol compatible with an external FIFO, therefore making use of an FPGA optional. Every MD-SiPM can deliver up to 64M time-stamps/s. The sensor can be arranged in any type of configuration through a dedicated synchronization input and can be used to operate jointly with an event generator, such as a pulsed laser, which is useful in many applications. Inherently compatible with 3-D-stacking technology, the sensor can serve as front-end electronics when it is used with a different SPAD silicon tear.