Transient faults in DRAMs: concept, analysis and impact on tests

Facilitating automatic test pattern generators using test point insertion

Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs

Tests for resistive and capacitive defects in address decoders

March tests for realistic faults in two-port memories

Functional memory faults: a formal notation and a taxonomy

Test point insertion for compact test sets

Industrial evaluation of DRAM SIMM tests

An experimental analysis of spot defects in SRAMs: realistic fault models and test

Impact of memory cell array bridges on the faulty behavior in embedded

Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy

Logical fault detection of CMOS SRAM ICs based on write quiescent supply current

Fault (in)dependent cost estimates and conflict-directed backtracking to guide sequential circuit test generation

Industrial evaluation of DRAM tests

Designing a memory module tester

Defining SRAM resistive defects and their simulation stimuli

Testability of the Philips 80C51 micro-controller

Illegal state space identification for sequential circuit test generation

The challenge of supplying quality DIMMs to the PC market

Industrial evaluation of stress combinations for march tests applied to SRAMs