Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs

Facilitating automatic test pattern generators using test point insertion

Transient faults in DRAMs: concept, analysis and impact on tests

Tests for resistive and capacitive defects in address decoders

Functional memory faults: a formal notation and a taxonomy

Test point insertion for compact test sets

An experimental analysis of spot defects in SRAMs: realistic fault models and test

Impact of memory cell array bridges on the faulty behavior in embedded

Industrial evaluation of DRAM SIMM tests

March tests for realistic faults in two-port memories

Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy

Designing a memory module tester

Illegal state space identification for sequential circuit test generation

The challenge of supplying quality DIMMs to the PC market

Defining SRAM resistive defects and their simulation stimuli

Port interference faults in two-port memories

Industrial evaluation of DRAM tests

Industrial evaluation of stress combinations for march tests applied to SRAMs

Fault (in)dependent cost estimates and conflict-directed backtracking to guide sequential circuit test generation

Logical fault detection of CMOS SRAM ICs based on write quiescent supply current