22 records found
1
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Transient faults in DRAMs: concept, analysis and impact on tests
Tests for resistive and capacitive defects in address decoders
Facilitating automatic test pattern generators using test point insertion
Impact of memory cell array bridges on the faulty behavior in embedded
Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy
Industrial evaluation of DRAM SIMM tests
Functional memory faults: a formal notation and a taxonomy
An experimental analysis of spot defects in SRAMs: realistic fault models and test
Test point insertion for compact test sets
March tests for realistic faults in two-port memories
Testability of the Philips 80C51 micro-controller
Industrial evaluation of stress combinations for march tests applied to SRAMs
Port interference faults in two-port memories
The challenge of supplying quality DIMMs to the PC market
Industrial evaluation of DRAM tests
Illegal state space identification for sequential circuit test generation
March tests for word-oriented two-port memories
Defining SRAM resistive defects and their simulation stimuli
Fault (in)dependent cost estimates and conflict-directed backtracking to guide sequential circuit test generation
