Transient faults in DRAMs: concept, analysis and impact on tests

Facilitating automatic test pattern generators using test point insertion

Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs

Tests for resistive and capacitive defects in address decoders

Impact of memory cell array bridges on the faulty behavior in embedded

An experimental analysis of spot defects in SRAMs: realistic fault models and test

Functional memory faults: a formal notation and a taxonomy

March tests for realistic faults in two-port memories

Test point insertion for compact test sets

Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy

Industrial evaluation of DRAM SIMM tests

Industrial evaluation of stress combinations for march tests applied to SRAMs

March tests for word-oriented two-port memories

The challenge of supplying quality DIMMs to the PC market

Logical fault detection of CMOS SRAM ICs based on write quiescent supply current

Port interference faults in two-port memories

Defining SRAM resistive defects and their simulation stimuli

Fault (in)dependent cost estimates and conflict-directed backtracking to guide sequential circuit test generation

Illegal state space identification for sequential circuit test generation

Industrial evaluation of DRAM tests