Fan-Out Panel Level Package has become a trend in Silicon Carbide MOSFET packaging due to its superior electrothermal performance and cost-effectiveness. However, the increased size of multi-chip embedded FOPLP packaging introduces greater challenges in sample preparation and thermal-mechanical stresses. In this paper, a large-sized (20mm*20mm*0.78mm) FOPLP with 4 SiC MOSFETs embedded is investigated. A three-dimensional thermal-mechanical numerical model is derived based on heat conduction and elasticity theories. It utilized analytical solution of Fourier temperature conduction and finite difference results for thermoelastic models to describe the temperature and deformation distribution during the FOPLP operation. It also reveals the heat coupling issue of multiple chips. Compared with the finite element simulation, the proposed method shows less than 2.5 % error in temperature and 2.3 % error in deformation. The computational speed is one-tenth that of the finite element method, while the memory usage is reduced to one-fifth. To mitigate the influence of chip thermal coupling on temperature and warpage, an optimized layout was employed to achieve temperature uniformity improvement. Finally, FOPLPs with the two layouts were fabricated. The warpage was monitored using a digital image correlation platform. To achieve the same temperature, the current required for the optimized layout was increased by 9 %. The warpage of the optimized layout at 60 °C was reduced by 13.5 %, and at 100 °C it was reduced by 14.7 %, validating the accuracy of the model and the significance of thermal-decoupling.

Optical micro-electromechanical systems (MEMS) demand exceptional precision, yet warpage during the die attach process on printed circuit boards can compromise performance. Here, a three-dimensional thermoelastic analytical model has been developed based on Fourier heat conduction and supported beam theory. This model facilitates the in-situ calibration of solder parameters via confocal micro-Raman spectroscopy, ensuring that the simulated dynamic evolution of warpage during soldering aligns closely with digital image correlation experiments. The results show consistence with Finite Element Method with error less than 1 % and time saving more than 60 %. Orthogonal experimental analysis further reveals that substrate thickness and thermal expansion coefficient variations are the primary factors affecting warpage, while chip area has a negligible role. Given the practical challenges in reducing substrate thickness, a stress-balancing strategy incorporating an additional transition layer is proposed, which is effectively validated with a high-resolution three-dimensional profilometer. This work provides valuable insights into the predictive modeling and warpage behavior characterization, directly supporting improved mitigation strategies in the die attach process.