In this thesis, we explore the physics and control protocols enabled by hopping spins in the quantum dot arrays. Our approach consists of experimental studies as well as numerical simulations. In chapter 2 we provide the background information relevant to the work in this thesis, including the theoretical description of spins in germanium quantum dots, as well as the measurement setup used in the experiments. In chapter 3 we study the control protocols for spin-spin exchange interactions, and quantify the individual coupling strength in a configuration of 2×2 array when all the nearest neighboring coupling are turned on. We can tune to a regime of equal coupling strength, in which the four-spin entangled states emerge as the resonating valence bond states. In chapter 4 we model the qubit frequency susceptibility to charge noise and predict the optimal magnetic field orientation for extended qubit coherence time. In chapter 5 we show multi-photon transitions in a two-spin system, and discuss opportunities to use this method for qubit addressability in large qubit array based on shared control architecture. In chapter 6 we demonstrate coherent spin qubit shuttling through quantum dots. We quantify the loss of the quantum information during the process. In chapter 7 we demonstrate high-fidelity baseband control of single qubit and two qubit gates, with extended coherence times by operating at low magnetic field. The single qubit gate is realized based on shuttling between the quantum dots, resembling the original spin qubit proposal by Loss and Divincenzo. The two-qubit CPhase gate achieves average fidelity 99.3% in the randomized benchmarking experiments. In chapter 8 we conclude and provide an outlook on the near future for germanium spin-qubits operations.
@en

The spin of a single electron or hole provides an attractive candidate for implementing a quantum bit when confined in a semiconductor quantum dot. Such a spin qubit is characterized by long coherence and short gate times. High-fidelity single and two-qubit operations have been demonstrated as well. Additionally, semiconductor quantum dots have a small footprint (~ 100 nm x 100 nm) and their fabrication employs techniques similar to processes commonly used in modern semiconductor technology foundries. This promises the realization of dense qubit arrays, leverage through industrial fabrication, and direct co-integration with classical control circuits.

Thus far, one-dimensional quantum dot arrays have been studied extensively. Yet, only by realizing two-dimensional quantum dot arrays the small footprint of quantum dots is fully exploited. Also, due to their small size quantum dots are extremely sensitive to their local environment and fabrication imperfections. In current devices, an individually tailored set of gate electrode voltages is required for each quantum dot to confine a single charge. The limited space available for routing these voltages on the device, coupled with the associated overhead in required voltage sources, presents a challenge in scaling quantum dot arrays, especially two-dimensional arrays.

This thesis focuses on two-dimensional quantum dot arrays and gate voltage uniformity. The first part (chapter 3 and 4) reports the realization of two-dimensional quantum dot arrays in a silicon/silicon-germanium (Si/SiGe) and a germanium/silicon-germanium (Ge/SiGe) heterostructure. Afterward (chapter 5 and 6), a novel all-electric method is presented to achieve increased homogeneity of the required gate voltages.

In chapter 3 a 2 x 2 quantum dot array in a Si/SiGe heterostructure is presented. It is tuned to be occupied by a single electron per quantum dot reaching the (1,1,1,1) charge state. Dedicated barrier gate electrodes on the device allow for controlling the interdot tunnel couplings between neighbouring quantum dots from about 30 ueV up to approximately 400 ueV as characterized through polarization line measurements.

In chapter 4 the focus is shifted towards a more scalable gate architecture for two-dimensional quantum dot arrays. It is inspired by random access architectures that are found in classical electronics. Specifically, a 4 x 4 quantum dot array in a Ge/SiGe heterostructure with shared gate electrode voltages is introduced. In this device, an odd charge occupancy is reached with either one or three holes in all 16 quantum dots simultaneously. Also, two shared barrier gate electrodes are placed between adjacent quantum dots. These enable selective control of the interdot tunnel coupling from less than 3 GHz to more than 10 GHz.

Spatial fluctuations in the electric background potential still limit the scalability of such a shared control array. Therefore, chapter 5 introduces a new method to increase the electrical uniformity in quantum dot devices. The presented method is based on applying stress voltages to the device gate electrodes. It enables the tuning of pinch-off voltages in quantum dot devices over hundreds of millivolts. Afterward, the new pinch-off voltages remain stable for hours at least. The method is used to homogenize the pinch-off voltages of the plunger gates in a linear array designed for four quantum dots. It reduces their spread by one order of magnitude from 153 mV to 20 mV.

Motivated by this demonstration, in the experiment presented in chapter 6 the stress voltage tuning method is applied to control the plunger gate voltages required to reach single electron occupation in a quantum dot array. In a double quantum dot, a stable (1,1) charge state is reached at identical and predetermined plunger gate voltage and for various interdot couplings. Finally, by applying stress voltages a 2 x 2 quantum dot array is tuned such that the (1,1,1,1) charge state is reached when all plunger gates are set to 1 V.@en

Spin qubit in semiconductor quantum dot arrays offers a promising platform for future scalable quantum computing with its small size and compatibility with modern semiconductor industry. To scale up the quantum dot arrays, one of the major challenges is the wiring bottleneck, as a high density of control lines might need to be integrated into a small chip. A proposal to solve this problem is using the shared control protocol, in which multiple qubits could be controlled by a shared line. For this, the most critical requirement is to realize uniformity across the quantum dot array, such that a single control signal could lead to an identical response in all dots involved. However, such uniformity is hard to achieve due to the variation of the device fabrication, and tackling this problem via materials and fabrication optimization only appears to be a daunting challenge.

In this thesis, we propose a potential solution to achieve uniformity of threshold voltage in such share-controlled systems. This solution is based on the hysteresis behavior of turn-on voltage in the heterostructure field-effect transistor (HFET) devices hosting the quantum dot array. In the Ge/SiGe HFET devices with hole as carrier, we found that the drift of turn-on voltage can be caused by population of 2DHG under negative gate voltage and reversed by applying positive gate voltage. We attribute this effect to trapping and detrapping processes on the dielectric surface of the device. Following this discovery, an automatic feedback control program was designed, in which gate voltage pulses are applied to control the trap filling level such that potential landscape in the device corresponds to the desired turn-on voltage. Using this program, we performed deeper investigations of the turn-on voltage shift including its relaxation and history-dependent stability. A hypothetical physical model for observations in these experiments is followed. For practical application of this effect, the feasibility to locally define and control the turn-on voltage is also demonstrated. Based on these results, we present a proposal for addressable manipulation of potential landscape in share-controlled quantum dot array, which might potentially realize the threshold voltage uniformity for scalable quantum dot array in the future.