In this article, we present an analytical formulation based on an equivalent circuit model to support the challenging task of designing and analyzing single-ended patch sensing elements to be integrated in planar technologies. The proposed approach further allows for differentiating the permittivity values of the individual layers when sensing over dense and stratified mediums. The equivalent model of the sensing pixel is derived resorting to equivalence theorem and transmission-line theory. The relative impact of the material under test and the metal thickness of the sensing element is accurately included in the evaluation of the endpoint load of the radial transmission line, equivalent to the patch radius. This approach of representing the single-ended sensing element isolates the capacitance contributions associated with the patch radius, patch thickness, and the medium under test. The computationally fast tool is further utilized in absolute permittivity measurements using a 0.14- μm CMOS 2-D permittivity imaging matrix prototype operating from 100 MHz to 2.9 GHz, reporting excellent agreement with theoretical values.

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We present a compact, scalable, and broadband architecture for the implementation of complex microwave permittivity sensors in complementary metal-oxide semiconductor (CMOS) technology. The proposed architecture consists of a patch sensor embedded in a programmable balanced readout bridge and performs third and fifth harmonic downconversion for fast multi-frequency readout. Circuits designed can act as the basic building block for a wide span of biomedical applications, ranging from wearables to permittivity imaging. Experimental results of manufactured prototypes demonstrate measurement noise reduction through bridge balancing, Debye model parameter estimation of independent material with a 1.6% error using full frequency dataset, and 5.3% in high energy efficiency mode, as well as image construction based on material permittivity differences.

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This paper presents a 0.15×0.3 mm² complex permittivity sensor integrated in a 40-nm CMOS node. A single-ended patch, employed as a near-field sensing element, is integrated with a double-balanced, fully-differential tunable impedance bridge that is driven by a square RF pulse. The multi-harmonic, interme-diate-frequency down-conversion architecture achieves a compact form factor and fast multi-frequency readout. Measurement results show good agreement with theoretical values and the measured relative permittivity variation remains below 0.3 over a 0.1-10 GHz range at a 1-ms measurement time. The energy efficiency resulting from the fast measurement time and the record-small active area allows integration in battery-operated wearables.

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A 0.14-μ m CMOS 2-D permittivity imaging matrix prototype operating at microwave frequencies is presented. It comprises 25 permittivity-sensing pixels, each consisting of a sensing patch connected to a dedicated RF bridge. A trans-conduct-ance stage converts the imbalance voltage to a current signal, subsequently down-converted to an intermediate frequency and sampled. The implemented sensor matrix shows precise permittivity measurements over a range of 0.1-10 GHz, and successfully demonstrates permittivity contrast with a resolution of 0.1 - 2.3 from 0.1 to 10 GHz when the matrix is interfaced with various dielectrics. Owing to the matrix implementation a sub-mm, permittivity discontinuity is easily resolved by the presented sensor device.

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In this contribution we present a new class of N:1 power combiner based on synthetic waveguides integrated in silicon technologies back-end-of-line. The input feeding is based on (N) E field probes employing capacitive resonance, feeding a waveguide with artificial dielectrics (ADs). The signal summation occurs on a single transverse plane, thus providing insertion losses which do not scale with the number of inputs. This results in a combiner more compact and without restriction in the number of inputs compared to the traditional power of two (2N) combiners. The power combiner operation is presented in a BiCMOS technology implementation and analyzed by means of full wave electromagnetic (EM) simulations. Finally, the experimental results of an integrated 4:1 back-to-back-combiner operating in the 240-310GHz band is presented and compared with the full EM model.@en

In this paper, we present a fully integrated RFDAC-based outphasing power amplifier (ROPA) in 40-nm CMOS that achieves 22.2 dBm peak output power with 49.2% drain efficiency at 5.9 GHz. It employs differential quasi-load-insensitive Class-E branch PAs that can dynamically be segmented using a 3-bit digital amplitude control word to improve efficiency at power back-off. At 8 dB back-off, this segmentation technique improves the ROPA drain and system efficiency by 5% and 7%, respectively, when compared to a non-segmented approach. @en