Quantum sensing technology has emerged as a promising field with superior sensitivity and accuracy in magnetic field sensing compared to conventional technologies. This breakthrough offers significant prospects in the biomedical sector, particularly in the realm of medical imaging.

This project focuses on the implementation of quantum sensing using an array of single Nitrogen Vacancy (NV) centers combined with an array of Single Photon Avalanche Diodes (SPADs). SPADs are available in various technologies and forms. To identify the optimal SPAD for this specific application, different SPADs with diverse parameters are designed on a chip using standard 40 nm TSMC process. These parameters include active area, active area shape and metal shielding.

The research aims to validate and characterize the performance of these distinct SPADs. However, during the validation tests, it was observed that the SPADs did not meet the criteria. The presence of ESD diodes on the chip introduced a low resistance current path, thereby hindering the characterisation process of the SPADs. Solutions to fix this problem and improve the system are provided.

The documented validation methods include general chip testing, establishing the I-V curves of the SPADs and avalanche and quenching testing. In addition, the characterisation methods for junction capacitance, dark count rate (DCR), photon detection probability (PDP) and time jitter are given.

For characterizing DCR and PDP a readout system is designed. It consists of an analog-to-digital converter (ADC), FPGA and Arduino. The data is communicated continuously to a PC. The ADC is not fully tested. On the other hand, the FPGA and Arduino are tested and verified to be sufficient for the DCR measurements. The readout system is too inaccurate for PDP measurements. A recommendation on how to make the readout system sufficient for PDP is given.

Highly accurate time sources, such as Cesium-based or GPS clocks, are the best candidates to provide a correct notion of time, but are too costly and impractical for implementation in every modern digital device. Ubiquitously, (crystal) oscillators are employed instead. To maintain a shared notion of time, the offsets and drift/jitter have to be compensated via the concept of synchronization, divided into time offset equalization and syntonization. Packet-based distribution protocols such as Network Time Protocol (NTP) and Precision Time Protocol (PTP) can provide time offset equalization, whilst synchronous Ethernet can deliver syntonization. To reach high synchronization accuracy, PTP and synchronous Ethernet can be combined into an improved protocol, referred to as White Rabbit. It enhances the one-way delay calculation through fine and coarse delay measurements. These improve PTP timestamps to reach sub-nanosecond synchronization accuracy.

The White Rabbit project has limitations though: it relies on extensive calibration parameter sets that are only available for limited devices and do not account for hardware variability. This is in contrast with the initial project objectives. Secondly, the update cycle of the hardware implementation is slow. Namely, the current White Rabbit switch is based on FPGA platforms from ten years ago. Thirdly, the switch contains costly components and requires full replacement of present network switches upon deployment.

This work opted to define a new switch design, which distributes the synchronization tasks over several smaller FPGAs to provide a low-cost implementation and improve applicability, whilst requiring minimal factory calibration and maintaining sub-nanosecond accuracy between devices.

The new switch concept is based on the smaller and widely applied White Rabbit node design. The proof of concept is based on two interconnected FPGAs forming a 1-port White Rabbit switch. Fine delay measurements, asymmetry estimations and fine delay compensations are applied to reach synchronization between the FPGAs. The Digital Dual Mixer Time Difference (DDMTD) is preferred for the fine delay measurements due to its superior resolution, area and invariance to large clock periods. A three-line asymmetry calculation is introduced and motivated to provide an improved one-way delay estimation. Lastly, the IDELAY element was selected to provide the fine delay compensation due to its process-voltage-temperature (PVT) invariance, negligible jitter addition and area demands.

Whilst both the fine delay measurement and fine delay compensation were thoroughly discussed by means of specifications and simulations, the three-line asymmetry calculation had to rely on a theoretical discussion. As such, measurements have shown that the transmission delay over an added bi-directional link is approximately equal when the clock signal moves from slave to master and vice versa. A large delay variability between other transmission lines is subsequently exposed. The variability leads to inaccurate one-way estimations with a traditional two-line approach. A three-line asymmetry calculation will be conclusively beneficial for the synchronization accuracy. The low-cost requirement of the distributed switch can be maintained through elimination of components in the slave and master node. The reduced switch lowers the hardware costs with approximately 25% by trading off cost-effectiveness with jitter filtering and consecutive performance.

This thesis describes the design and implementation of a controller and GUI for an AI loudspeaker filter design program. This program uses a genetic algorithm to create a combination of analog passive filters, one for each driver in a loudspeaker system. In the controller, two cost functions are designed to evaluate these filter combinations, and when the genetic algorithm has created its final filters, unnecessary components are removed and all component values are optimized. A GUI is created to allow easy user interaction.
For selecting a cost function, not enough data was obtained to make a deliberate decision based on performance. Therefore, this decision was based on theory and subordinate features. Nonetheless, the final program is able to create flat acoustic responses in a margin of 2 dB.

RISC-V is an open-source Instruction Set Architecture that offers a simple, modular, and scalable design. Its extensions allow for customization and optimization based on specific execution workloads. One of these workloads could be quantum computing, which exploits the concepts of superposition and entanglement to manipulate qubits and perform computations that would be infeasible for classical computers. The customization offered by RISC-V presents a remarkable opportunity to develop specialized architectures that can efficiently address the execution of quantum algorithms, bridging the gap between classical and quantum computation.
In this thesis work, a RISC-V 32-bit instruction set extension called qRV32 is developed to address the control of diamond qubits, based on an existing QISA. The architecture defines the encoding syntax for the machine-level instructions and the exchange protocol for control and data in the system. Accordingly to this specification, the hardware of a control core processing the ISE has been designed. Custom functional units and necessary peripherals have been added to the base core CV32E40P in order to implement the desired control functionalities. The thesis also proposed additional work to ease the complete design and functionality of the system. In particular, an assembler targeting qRV32 has been developed, enabling the automated translation of assembly instructions to machine-level code. Furthermore, an experimental model is developed to evaluate the parallelism of the system.
The resulting architecture is eventually tested and evaluated. Software simulations are used to test the functionality of the control core and the custom components. Eventually, a simplified version of the model is used to estimate the parallelism of the core, which can control 23605 network nodes when operating at fclk = 55MHz.

As electromagnetic waves cannot propagate sufficiently far in water, underwater communication is mainly performed using either acoustics or optics. However, none of these technologies have been proven to be completely effective in every situation. Therefore, research in new underwater communication systems can still bring large benefits to a wide range of different underwater technologies.
During this project, a promising new type of underwater communication system based on electric fields has been investigated. While two subgroups have been working on the characterization of the communication channel and different modulation techniques, this thesis focuses on the hardware needed for optimal communication. Moreover, this hardware includes both a low-noise receiver and a high power transmitter. An analysis of different design options, the detailed design of one of these options and the validation of the design are given in this report. However, to get a complete overview of the designed communication system and its performance, it is recommended to also read the other two thesis reports.

With the requirements for CubeSats increasing, a push towards utilizing high­performance equipment has never been greater. Incorporating these equipment in an environment that is cost­, space­ and power­constrained, is challenging. Simultaneously, high­performance equipment require high pointing­accuracy and low­jitter. This thesis proposes the use of a cost­effective reaction­wheel, which utilizes three hall­sensors for accurate attitude­control. Additionally, the requirements state that the reaction­wheel operates in the low­speed region, whilst tracking low­acceleration commands. For this, a controller­structure is designed, simulated & implemented in order to provide accurate angular­velocity estimates at a constant rate. Whilst the angular­velocity estimates are within 1% of the measurements, the angular­acceleration tracking performance relies greatly on the noise of the reaction­wheel torque­friction. Nonetheless, the angular­acceleration mean error was found to be 0.005 RPM/s, with a variance of 0.3 RPM/s on a 0.01 RPM/s reference

The urgency for high-security products for industrial networks is increasing as malicious hackers are improving their accessibility tools. A common practice for a company to protect its sensitive data is network segmentation. The network is segmented in different domains with distinctive security levels. The sensitive data is stored and managed within the domain of the highest security level. To access this domain from another domain of a lower security level, a highly reliable connection is required. You want to have full control over the incoming and outgoing data flow between these network segments. A variety of solutions provide a highly-secured connection to link those segments which differ in range of features and control. An upcoming trend is the network diode. This device will allow data flow in only one direction. All the flows going into the opposite direction are being blocked. However, to feature an arbitrary flow between two network segments, the diode should consist of a numerous amount of properties. To narrow down the optional features a network diode should provide, this thesis will focus on TCP streams. TCP is one of the most common protocols used in internet traffic. Furthermore, TCP is a challenging protocol as it is a connection-oriented bidirectional protocol, which is intrinsic controversial with the concept of the data diode. To ensure the security of the data diode, this thesis will focus on a complete hardware design of the data diode. Software inside the data diode is still a risk for a security breach. This thesis will investigate the critical operations of TCP to implement them in the data diode. The aim is to utilise TCP's characteristic operations of the acknowledgement managing, the sliding window system, the congestion control algorithm, and explores the advantage of existing TCP options. To evaluate the feasibility of a high performance data diode featuring TCP, the system is broken down to project the behaviour of a TCP stream on a one-way connection device. This results in two separate TCP connections, with only the precious data as common shared information. This model requires a buffer at one side of the diode to transmit data in a TCP stream. To analyse and examine the influence of the diode configuration to the size of the buffer, a diode module is created to simulate in a OMNeT++ environment. From this simulation tool, a minimal set of parameters can be extracted that are essential to configure the data diode. With the assumption of having control on the network management at the trusted side of the diode, a configuration without a congestion control algorithm and without adding radical TCP options is recommended to minimise the required buffer size. Thereafter, this thesis proposes a high-level hardware design to implement the data diode on a hardware project. The design focuses on the high data rate which should be available to satisfy the data diode's requirements. Finally, this thesis concludes with an elaboration on the assumptions of the limitations of the network environments and recommends features to implement in future work.

Recently, interest in the use of deep learning technology for RF applications has increased. However, many of these studies are focused on developing deep learning models for a particular RF application. Therefore this master thesis focuses on the implementation of these kinds of deep learning models by using FPGAs such that these deep learning models can be used in an FPGA-based Software Defined Radio.

In this master thesis, a custom FPGA accelerator is designed for CNN models using reusable and configurable building blocks. The accelerator employs a streaming architecture and is fully pipelined, such that it accepts new input data every clock cycle. A key design aspect is that all building blocks in the accelerator are designed to be able to work on a portion of its input data. The implication is that the building blocks can produce an output as soon as enough input data is available. As a result, the work that the building blocks
have to performis spread out over time and thememory required for storing data is also reduced. Moreover, the precision of the fixed point parameters and operations is configurable. Therefore there is no limitation of only specifically supporting binary or ternary operations.

This accelerator has been tested for the automatic modulation classification problem. The result is an accelerator that can process real-time data at 600MHz and consume fewer FPGA resources than other similar initiatives. In a direct comparison with hls4ml, the designed custom accelerator achieves 2.4 times higher throughput and 2.3 times lower latency for the identical CNN, while also achieving the same accuracy and significantly lower resource utilization. In addition, the custom accelerator is compared to a ternary neural
network FPGA accelerator formodulation classification as proposed by Tridgell et al. The custom accelerator uses 3.3 times fewer LUTs, 9 times fewer FFs, 4 times fewer DSPs, and uses no BRAM, while the accelerator proposed by Tridgell et al. uses 48.5% of the available BRAM in an RFSoC FPGA.

This report focuses on the design and implementation of both a detection system and an enclosure, which are designed to be used in a quantum random number generator. These parts are designed to be manufactured using off-the-shelf components to make the quantum random number generator affordable and accessible to a completely new user-group that cannot afford and operate the currently existing alternatives for quantum random number generation. After implementing the designed systems it is found that although the output of the system is random, true-randomness cannot be guaranteed using off the shelf components, because of the interference of classical noise sources.

Nowadays, the need for better and faster computing searches for solutions in the field of quantum computing. It is believed that quantum computing can and will surpass conventional, classical computing. When quantum computing surpasses classical computing, it is called quantum supremacy. There are many different projects that use different quantum technologies aim to achieve quantum supremacy, such as projects from Google and Intel. In this thesis, the reader is introduced to a new project: the Fujitsu Project. The project is a collaboration between TU Delft and Fujitsu and has the goal of fabricating a new distributed quantum quantum computer based on color centers in diamond. The focus of the thesis is the definition of the microarchitecture.

The quantum computer stack is explained in detail. Precise and robust definitions for each of the seven layers of the quantum computer stack are given, where the definition of the microarchitecure is most important. A microarchitecture is defined as the list of instructions of the lowest level before entering control electronics. To define the diamond microarchitecture, a set of goals have to be completed. Other architectures such as QuTech's QuMA and QuTech's Central Controller were identified and analyzed. Combined with the requirements of the overall diamond system architecture as defined by the project, a list of requirements for the microarchitecture is created. Using these requirements, a Quantum Instruction Set Architecture (QISA) and a microarchitecture are defined.

Based on the defined QISA and microarchitecture, a compiler is designed. The compiler is made in OpenQL. OpenQL is a framework for high-level quantum programming that targets different quantum computing platforms. The main task of the compiler is to translate high-level quantum algorithms, expressed in a high-level quantum programming language (C++/Python APIs), to quantum microcode. The quantum microcode consists of instructions that are defined in the microarchitecture.

The QISA, microarchitecture and compiler are verified against the requirements that are set at the beginning of their respective definition phases. The microarchitecture supports for all gates that are part of cQASM 1.0. In addition, it supports all diamond color center specific protocols and rules. The compiler supports all instructions from cQASM as well. Moreover, the compiler supports all standard (gate) instructions and diamond specific instructions through OpenQL's Python API.

The work is intended to be a solid baseline, where the future of the project can rely and improve upon. Possible improvements could be the adaption of the microarchitecture to the growth of the number of controlled qubits per controller, the parallelization of the microarchitecture instructions to improve instruction throughput, and alignment with the quantum network group. The compiler can also be improved with for example enhanced scheduling, differentiation between qubit types and an entanglement library. The next step in the design of the microarchitecture will be the design of a microarchitecture simulator, which takes the microcode as input and simulates the hardware architecture.

The human brain is a natural high-performance computing systemwith outstanding properties, e.g., ultra-low energy consumption, highly parallel information processing, suitability for solving complex tasks, and robustness. As such, numerous attempts have been made to devise neuromorphic systems able to achieve brain-akin computation abilities, which can aid in understanding the complex human brain functionality and can be utilized to solve complex problems, e.g., pattern recognition and data mining. However, the fact that human brain comprises billions of neurons, which are the fundamental information processing units, and trillions of synapses that interconnect them makes the design and implementation of large-scale brain-inspired computing systems quite a challenging task. Graphene appears to be a promising candidate for scalable neuromorphic implementations as it exhibits a wealth of outstanding properties, e.g., ballistic transport, ultimate thinness, flexibility, and graphene devices are capable of emulating complex nonlinear functions and can be readily tuned to provide various conduction dynamicswhile preserving low energy operation and small footprint. Moreover, graphene is biocompatible, which offers perspectives for graphene-based neuromorphic bio-interfaces. This thesis aims to investigate graphene’s potential to enable scalable and energy effective neuromorphic computing. To this end, we first introduce an atomistic-level simulation model for calculating graphene electronic transport properties, that captures the hysteresis effects induced by interface charges trapping/detrapping phenomena. Second, we propose a generic graphene based synapse, which can be tailored to emulate different synaptic plasticity types by properly modifying its Graphene NanoRibbon (GNR) shape and contacts topology, as well as applying external voltages. Subsequently, we introduce a compact graphene-based integrate-and-fire spiking neuron that mimics the basic spiking neuronal dynamics. We further propose a basic SpikingNeuralNetwork (SNN) unit,which can be utilized to implement complex graphene-based SNNstructures. Finally,we introduce a reconfigurable graphene-based SNN architecture and a training methodology for obtaining the initial SNN synaptic weight values. We demonstrate the feasibility of the synaptic weights training methodology and the practical capabilities of the proposedSNNarchitecture by applying them to solve character recognition and edge detection problems. Our experiments clearly indicate that the proposed graphene-based neuromorphic approach enables lowenergy operation at small chip real estate footprint, which are enabling factors for the realization of scalable energy-efficient SNN implementations. @en

In the recent years the satellite industry has progressed on the subject of optical communication for use in space. With recorded speeds over 5 Gb/s it has shown to be an alternative for radio communication. In the CubeSat market this technology is new, underdeveloped, and could lead to new missions that were not possible before. As such, TNO and Hyperion joined forces to create the CubeCAT LCT (Laser Communication Terminal). The core part of this LCT is the high-speed digital data path, which was not implemented. This thesis discusses the design, implementation, and verification of the high-speed data path of the CubeCAT LCT (Laser Communication Terminal) that has a targeted speed of 100 Mb/s, with a future upgrade path to 1 Gb/s. The CubeCAT module consists of multiple modules, of which the DMU (Data Management Unit) hosts the high-speed data path. As the DMU was not implemented, a design for the DMU is proposed in this thesis. For this design multiple architectures, interconnects, and components where considered. The proposed design is based on an Hyperion CP400.85 microprocessor connected to a Lattice ECP5-5G FPGA, together with extra external memory and external storage. Then, an implementation of the high-speed data path was made that is based on a QSPI link between the microprocessor and the FPGA. This implementation is based on streaming the data from the microprocessor to the FPGA, in which the data is encoded according to the TNO3k FEC (Forward Error Correction) scheme. After encoding, the data is outputted as an LVDS signal to the laser output. The implementation of the high-speed data path was verified by simulation and on a development setup. This was done by first verifying all submodules, with focus on the QSPI link and the TNO3k encoder, and then as a whole system. All submodule tests were successful, with a note to the verification of the QSPI link. It was found that the development setup was limited to a SPI frequency of 41.50 MHz due to signal integrity issues. During the system test it was found that the there was a lack of LVDS test material. As such the LVDS output was replaced by a UART output. With this output the whole system has been validated for a QSPI link speed of 119.2 Mb/s and an internal FPGA speed of 3.2 Gb/s. The system, with LVDS output, is estimated to consume 1 watts of power. With the validation of the whole system, the high-speed data path of the CubeCAT LCT has been implemented. The design of the DMU allows for a later, 1 Gb/s upgrade of the high-speed data path.

As CMOS feature size is reaching atomic dimensions, unjustifiable static power, reliability, and economic implications are exacerbating, thus prompting for research on new materials, devices, and/or computation paradigms. Within this context, Graphene Nanoribbons (GNRs), owing to graphene’s excellent electronic properties, may serve as basic structures for carbon-based nanoelectronics. However, the graphene intrinsic energy bandgap absence hinders GNR-based devices and circuits implementation. As a result, en route to graphene-based logic circuits, finding a way to open a sizable energy bandgap, externally control GNR’s conduction, and construct reliable high-performance graphene-based gates are the main desideratum. To this end, first, we propose a GNR-based structure (building block) by extending it with additional top gates and back gate while considering five GNR shapes with zigzag edges in order to open a sizeable bandgap, and further investigate GNR geometry and contact topology influence on its conductance and current characteristics. Second, we present a methodology of encoding the desired Boolean logic transfer function into the GNR electrical characteristics, i.e., conduction maps, and then evaluate the effect of VDD variation on GNR conductance. Moreover, we find a proper external electric mean (e.g., top gates and back gates) to control the GNR behavior. Third, we develop a parameterized Verilog-A SPICEcompatible GNR model based on Non-Equilibrium Green’s Function (NEGF)-Landauer formalism that builds upon an accurate physics formalization, which enables to symbiotically exploit accurate physics results from Matlab Simulink and optimized SPICE circuit solvers (e.g., Spectre, HSPICE). Subsequently, we construct graphene-based Boolean gates by means of two complementary GNRs, and design a GNR-based 1-bit Full Adder and a SRAM cell. Finally, we extend the NEGF-Landauer simulation framework with the self-consistent Born approximation while taking into account the temperature-induced phenomena in GNR electron transport, i.e., electron-phonon interactions for both optical and acoustic phonons, and further explore the graphene-based gates performance robustness under temperature variations.@en

The goal of this project is to identify the most promising measurement method and strategy for measuring the thickness of grease and to design a sensor module with electronic read-out and communication module. This project has been split into two parts: a sensor implementation and a communication system. This report describes the design and implementation of the communication module and power supply. The communication module has been designed to work conform a master-slave principle using MODBUS over an RS-485 databus. The used hardware for the communication module is rated to work within a desired 1 to 100m range. Furthermore the master node is connected to the internet to present the data on a small webserver. The power supply design depends on the implementation of the sensor, and contains the use of linear voltage regulators and inverters. The results show that the communication module works properly, whereas the power supply requires some further work.

Pavlovian eyeblink conditioning is a powerful experiment used in the field of neuroscience to measure multiple aspects of how we learn in our daily life. To track the movement of the eyelid during an experiment, researchers traditionally made use of potentiometers or electromyography (EMG). More recently, the use of computer vision and image processing alleviated the need for these techniques, but currently employed methods require human intervention and are not fast enough to enable real-time processing. We selected a combination of face and landmark-detection algorithms in order to fully automate eyelid tracking, and accelerated them to make the first step towards an on-line implementation. Various different algorithms for face detection and landmark detection (eyelid detection) are analyzed and evaluated. Based on this analysis, two algorithms are identified as most suitable for our use case: the Histogram of Oriented Gradients (HOG) algorithm for face detection and Ensemble of Regression Trees (ERT) algorithm for landmark detection. These two algorithms are accelerated on GPU and CPU, achieving speedups of 1753× and 11.49×, respectively. A combination of these algorithms is successfully implemented for a real neuroscientific use-case: eyeblink response detection, achieving an overall application runtime of 0.533 ms per frame, which is 1067× faster than the sequential implementation. Furthermore, this accelerated implementation was used to generate a database of 1440 eyeblink responses during the conditioning experiment. We made use of multiple machine-learning techniques to analyze this database and concluded that there is a correlation between the asynchronicity of the eyelids and the eyeblink-response performance during the conditioning experiment.

The ρ-VEX is a runtime reconfigurable VLIW processor. It is able to exploit both ILP as well as TLP by running one program in multiple lanes, or several programs concurrently. To accurately quantify its performance compared to other processors, it is implemented as an IC.
A fully automatic scripted flow is described, constructing an optimized, error-free ASIC. The design area is limited to 3.5 um², to allow it to be manufactured with the cheapest 65 nm prototyping run available at IMEC. In order to achieve this small design area, a new 24-port register file design has to be devised. In its current state, it is implemented using standard logic cells. Clever optimizations involving cell padding and minimum overhead power routing are necessary to reduce a total routing overcongestion from 7% to zero.
This implementation is expected achieve a clock speed of 141 MHz, only limited by the ρ-VEX reconfiguration logic. By lowering the frequency to 100 MHz, the energy dissipation is reduced by 96%, to a total of 367 uW/MHz. This is comparable to similar VLIW designs. Using LVDS communication clocked at four times the core frequency, a data bandwidth of 4 Gbit/s is achieved using only 26 external pins. This allows the main data and instruction memory to reside off-chip.
To ensure a correct design, it is verified using DRC, LVS, and ERC. For improved reliability, IR-drop is kept within 1% of the core voltage, using minimal power routing. Furthermore, the effect of electromigration is kept extremely low such that the mean time to failure on nets is 90 years.
The scripted flow will aid in prototyping, allowing accurate estimates to be calculated in a mere 7% of the original time. Proposals for a future design are expected to reduce the register file area and power dissipation by more than 40%. By improving the pipeline and shortening the critical path, a two to four fold improvement in clock speed can be expected, without adversely affecting power dissipation.

An increasing amount of critical applications use DRAM as main memory in its computing systems. It it therefore extremely important that these memories function correctly during their lifetime in order to prevent catastrophic failures. Already during the design phase, the reliability of the circuit needs to be predicted so that a reasonable lifetime expectation can be given. Although the importance of reliability analysis is clear, in literature not much research on DRAM reliability is available to designers. This thesis proposes a two phased
DRAM reliability prediction model that can be used in the circuit design phase. During the first phase, the circuit performance is analyzed for different wear-out mechanisms affecting different subcomponents in the design. In the second phase, the results of the first phase are then used to determine the reliability of the circuit.
In the first phase, the wear-out effects of Bias Temperature Instability (BTI) Hot Carrier Injection (HCI) and radiation trapping as well as transistor mismatch are examined. BTI is modeled using the RD-model, HCI with the lucky electron model, transistor mismatch with Pelgrom’s model. Wear-out caused by radiation
trapping is modeled as Gate Induced Drain Leakage (GIDL), the data for which are derived from retention time degradation measurements of an irradiated commercial DRAM. The circuit performance is analyzed per subcomponent of the DRAM design in a range of different metrics. Furthermore, the aging effects on a
dwonscaled version of the circuit are investigated.
In the second phase, reliability functions are derived from the results from phase one per wear-out mechanism and per subcomponent. These reliability functions are used in an analytical reliability model which yields the overall circuit reliability.
The results from the first phase show degradation of the retention time as well as degradation of sensing delay metrics. Due to the relative low duty factor of memory cells, BTI and HCI have minor impact on the memory cell circuit performance. Radiation however, renders the circuit useless once the Total Ionizing Dose (TID) becomes more than 126 krad. On other subcomponents than the memory cells, BTI and HCI shift the reference voltage which results in an increase of retention time. BTI and HCI stressing of the sense amplifier
also slightly increases retention time but mainly increases sensing delay. For both reference cells and the sense amplifier it holds that higher radiation doses break down the circuit completely. The same effects hold for the downscaled circuit, although the observed effects are more severe than in the unscaled device.
The system reliability prediction in the second phase shows the importance of individual reliability prediction of the subcircuits and wear-out mechanisms. Via the individual analysis, it becomes clear that the system reliability is mostly impacted by the degradation of the sense amplifier delay due to BTI and HCI. Other metric variations, like the increase in retention time caused by the reference cells, have less impact. It was found that the system reliability decreases to 0.84 after 1·10⁸s at a stressing temperature of 300K.