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Nicolo Bellarmino

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3 records found

Orienting to SPICE and Circuit Design

Journal article (2026) - Changhao Wang, Sicong Yuan, Nicolo Bellarmino, Danyang Chen, Hanzhi Xun, Lin Wang, Mottaqiallah Taouil, Moritz Fieback, Said Hamdioui, More Authors
Physics-based compact models for emerging non-volatile memories (NVMs) are often limited by the complex interactions of microscopic domains and defects that are difficult to capture analytically, resulting in reduced accuracy and simulation efficiency. To address this challenge, a machine learning (ML)-based approach is proposed using artificial neural networks (ANNs) trained entirely on device measurement data, enabling a direct translation of fabrication characteristics into SPICE-compatible circuit models. The resulting models achieve high accuracy (MSE: 0.724, adjusted R2 : 0.998), significantly outperforming physics-based baselines with an 18× lower MSE for polarization and a two-order-of-magnitude precision improvement in FeFET current simulation, while accurately capturing the wake-up process. Furthermore, the model demonstrates robust out-of-distribution (OOD) extrapolation to unseen ferroelectric thicknesses and a 33.7% improvement in simulation speed. These results validate the ML-based approach as a highly efficient, SPICE-compatible solution for next-generation memory. ...
Conference paper (2025) - Changhao Wang, S. Yuan, More Authors..., N Kolahimahmoud, H. Xun, Nicolo Bellarmino, Danyang Chen, Chujun Yin, M. Taouil, M. Fieback, S. Hamdioui
Ferroelectric Field-Effect Transistors (FeFETs) are promising candidates for non-volatile memory (NVM) technologies, especially in embedded systems and edge computing. However, due to their physical characteristics, FeFETs exhibit unique defects—such as Threshold Voltage Shifting (TVS) caused by trap charges in the oxide layer—that are not captured by conventional defect models. This study adopts the Device-Aware Test (DAT) methodology to model these defects by incorporating their impact into the electrical parameters, calibrated using measurement data. Defect injection, circuit-level simulations, and fault analysis are performed to derive realistic fault models. Finally, the March algorithm and Design-for-Test (DfT) techniques are proposed to effectively detect these defects. ...
Conference paper (2025) - Sicong Yuan, Changhao Wang, Said Hamdioui, Moritz Fieback, Hanzhi Xun, Mottaqiallah Taouil, Xiuyan Li, Danyang Chen, Lin Wang, Nicolo Bellarmino, Riccardo Cantoro
The development of Ferroelectric Field-Effect Transistor (FeFET) manufacturing requires high-quality test solutions, yet research on FeFET testing is still in a nascent stage. To generate a dedicated test method for FeFETs, it is critical to have a deep understanding of manufacturing defects and accurately model them. In this work, we introduce the unique defect, Anomalous Charge Trapping (ACT), in FeFETs. The ACT-defective FeFET is characterized, and the physical mechanism of the defect is explained. Then, we apply the Deviceaware Test (DAT) method to design a specific ACT-defective FeFET model, which includes the physical impact of the defect on the electrical parameters of defect-free models, and calibrate the model with measurement data. Fault modeling is performed based on circuit-level simulations, and dedicated test solutions are proposed. ...