As classical computing paradigms approach their physical limits, quantum computing has emerged as a promising solution capable of solving certain complex problems with substantial speedup. However, before quantum computers can be deployed in real-world situations, they must be able to scale up to thousands of qubits with high fidelity while maintaining the ability to accurately and precisely control each qubit. This requires a part of the digital control logic placed close to each qubit that orchestrates the control signals sent to each qubit -- the local controller. This thesis focuses on the design and implementation of this local controller for operations on diamond qubits, building on top of an existing control architecture, from specifying the design requirements to actual hardware implementation and verification.

Multiple contributions are made in this thesis towards realizing a fully functional local controller design. The required functionalities for full support of all quantum operations are identified. Based on these functionalities, the designs of the new components and microinstructions are proposed. These designs are implemented as microcode and circuit architectures. In this process, a control sequence and relevant architecture for entanglement generation between color centers are proposed and implemented. An improved communication scheme with the network of local controllers has also been implemented to meet functional requirements and facilitate performance improvements. The new implementations are verified and prototyped on an FPGA performing actual quantum operations, demonstrating that the local controller is capable of performing all types of quantum operations with sufficient accuracy and precision, integrating seamlessly with peripheral components in the quantum control layer.

The work of this thesis represents a major step forward in the microarchitectural stack of a diamond quantum computer, paving the way toward the realization of large-scale quantum computing capable of addressing practical, real-world problems.

Transformers are widely used in power electronics but their low operating frequency typically makes them bulky. Increasing the switching frequency can significantly reduce transformer size, weight, and production costs, which is particularly advantageous for portable applications such as chargers. This report investigates the operation of high-frequency transformers and presents the design and development of a working prototype operating at up to 3MHz.
Electrical parameters, including inductance, capacitance, and resistance, were measured using a Bode 100 vector network analyser (VNA) and validated through analytical models and finite element simulations in COMSOL Multiphysics. Based on these parameters, a transformer model was constructed using IEEE Std 390 [1] and verified in LTSpice against measured results. Toroidal cores made of soft ferrite materials in various sizes were evaluated, and round copper wire was initially used for windings. To minimize AC resistance at high frequencies, litz wire was selected for the final prototype. The completed transformer was integrated into a switching circuit operating at 1.5MHz, demonstrating successful high-frequency performance and practical viability.

In network science, numerous studies based on the complementarity principle have emerged
since 2018 [1]. Unfortunately, theoretical foundations of complementarity are still in their infancy. Recently, a synthetic complementarity-based model called Complementarity Random
Hyperbolic Graph (CRHG) has been proposed. CRHG model was assumed to explain the topological properties of real complementarity-driven networks. In other words, this model could serve as a foundation for studying complementarity mechanisms in networks.The main goal of this thesis is to address the knowledge gap: although a complementarity-based network model has been proposed in previous studies, its topological properties have not been systematically examined. To fill in this gap, this work systematically studies complementarity network models (CRHG, GCRHG) and documents their topological properties. Moreover, we interpret the topological properties as a function of the network model parameters. We find that the CRHG model exhibits three fundamental properties: Scale-Free property, Small-World property, and Non-vanishing bipartite clustering. It indicates that it is a unique combination compared to other synthetic models. Its unique complementary connectivity mechanism makes it particularly effective for modelling complex networks formed by the complementarity mechanism. Furthermore, we also study and investigate a generalized synthetic model called Generalized Complementarity Random Hyperbolic Graph (GCRHG). We measure and analyze its clustering and bipartite clustering properties. We find that this model allows for smooth turning between similarity and complementarity. Overall, we document and interpret the topological properties of simulations for complementarity-based spatial graph models. Additionally, we conduct partial simulation verification of the theoretical topological properties of synthetic complementarity-based models, providing a reference for their future development and applications.

This thesis investigates the robustness of Gate Set Tomography (GST) under the influence of time-correlated (non-Markovian) noise. GST is a widely used protocol for characterizing quantum gates, yet its efficacy traditionally relies on the assumption of Markovian noise, where errors are memoryless. This research challenges this assumption by introducing non-Markovian noise into simulated GST experiments using a custom-developed Python library. The study com- pares baseline GST performance under Markovian noise with GST results un- der various non-Markovian noise conditions. The findings highlight significant discrepancies in GST’s error reporting and reveal a distinct trade-off between GST’s accuracy and consistency in practical, non-Markovian settings. This work contributes to the broader understanding of error characterization in quantum computing and provides a robust framework for future studies in quantum gate fidelity under realistic noise conditions.

This thesis details the design and development of the Power System for the Rover Deployment System. This power system delivers and manages the necessary power required by the entire Rover Deployment System. The RDS is responsible for ensuring the rover’s survival inside the transportation pod during transit. It also handles releasing the rover, which a mechanical mechanism will lower onto the lunar surface. The goal of Lunar Zebro is to send a nanosatellite to the moon for lunar surface exploration and radiation measurements. The power system was designed to power the MCU and transceivers at 3.3V, to provide power for rover charging at 12V, and to charge a capacitor bank used to provide the necessary actuation power to the NEAs. An electrically triggered umbilical release mechanism, unfortunately, could not be implemented due to a lack of available data. The circuit for this system was created, simulated, and added to the PCB design of the RDS. The simulations of the circuit behaved desirably. Due to the lead time on orders, the PCB has unfortunately not been received yet. Because of this, the entire power system has unfortunately not been tested yet.

Artificial Intelligence has become a dominant part of our lives, however, complex artificial intelligence models tend to use a lot of energy, computationally complex operations, and a lot of memory resources. Therefore, it excluded a whole class of hardware in its applicability. Namely, relatively resource-constrained low-cost hardware. This paper investigates learning methods that are potentially better suited for these types of devices: the forward-forward algorithm and Hebbian learning rules. The results are compared to backpropagation with equivalent network configurations, training hyperparameters and internal data types on different types of low-cost hardware. Backpropagation has consistently outperformed other algorithms in various tests. It exhibits higher accuracy, faster training, and faster inference compared to forward-forward models. However, forward-forward models can come close to matching backpropagation's performance, but they suffer from longer training times and decreased performance with multi-layer networks. Additionally, a poorly trained forward-forward model is sensitive to quantization, resulting in a significant drop in accuracy. On the other hand, forward-forward models offer the benefit of independently training each layer, allowing for more flexibility in optimizing the training process. Hebbian models were not found to be competitive, displaying performance below the required threshold. Smaller models for MCU and FPGA would likely perform even worse.

Quantum computing is a promising means of satisfying the ever-increasing need for more and faster computations. While some specific applications can already benefit from quantum computing today, a large-scale general-purpose quantum computer is yet to be developed. Many different technologies are being explored to reach this goal, color centers in diamond being a promising candidate. This thesis focuses on a specific kind of color center: the nitrogen-vacancy center (NV center).
Building on top of existing work, a quantum instruction set architecture (QISA) for a quantum computer based on NV centers is designed. A compiler targeting this QISA is designed and implemented using the OpenQL framework. In this process alternative approaches are also explored and contributions useful outside the context of NV centers are made. The final compiler is able to take a quantum circuit operating on logical qubits and transform it into a sequence of QISA instructions operating on physical qubits. This functionality integrates seamlessly with the existing passes in OpenQL, allowing for further extension and the possibility to make use of future developments.
Additional functionality includes optimization, scheduling, and hardware-oriented features such as quantization of operands. Each step is easily configurable using a multitude of scripts and data files, and additional steps can be added in the future if needed.
The functionality of the developed compiler is demonstrated by compiling several circuits, some of which are validated by passing their output through a simulator.
The compiler configuration as used in these tests is able to transform logical circuit into simple physical circuits, but the compiler provides all the functionality to use more complicated logical qubits which incorporate quantum error correction.

RSA encryption standard is a vital component of everyday internet communication. It is currently seen as being unbreakable as the problem that it is based on, semiprime factorisation, is an NP problem. Therefore, to try and break RSA using the current state of the art factoring method will take thousands of years. However, thanks to the advent of quantum computers we do know that RSA can theoretically be broken in seconds in two main ways. Firstly, by using Shor’s algorithm. Secondly, by formulating it as a binary optimisation problem and solving the formation with the quantum approximate optimization algorithm or solving the formulation by using quantum annealing. Unfortunately, there does not exist a quantum computer today that is accurate nor large enough to be able to break RSA encryption any time soon. For example, the largest semiprime number that has been factored by a quantum computer was a 41-bit number, as opposed to 2048-bit numbers that get used for RSA encryption. Fortunately, what is possible is to split the binary optimisation problem formulisation up into sub- problems, solve them individually and combine the solutions to get the answer, as shown in Wang et al. . Unfortunately, how the Wang et al. approach splits the problem up is not scalable, as when the problem gets larger so do the subproblems. Therefore, in the end the subproblems will expand to such a size that even they cannot be solved. The problem of ever expanding subproblems is the main focus of this thesis. We present a new approach that splits the problem into subproblems that are of constant size. Consequently, no matter how large the problem gets, all components can still be solved. Using our new method, we have been able to vastly outperform previous records set by quantum computers. However, our approach does not outperform current state of the art classical factoring methods. However, we also show that our new approach has limits. The increase in the amount of subprob- lems means an exponential increase in the spatial complexity when combining the solutions. Fortunately, we also present ways in which we can reduce the spatial complexity. These methods have a mixed success. However, they have meant that we can factor numbers that have more than triple the bit length than if we were not to use them. Finally, our techniques in reducing the spatial complexity have led us to discover a new weakness in RSA encryption. Therefore, potentially wreaking havoc on the security of the internet.

Nowadays, the need for better and faster computing searches for solutions in the field of quantum computing. It is believed that quantum computing can and will surpass conventional, classical computing. When quantum computing surpasses classical computing, it is called quantum supremacy. There are many different projects that use different quantum technologies aim to achieve quantum supremacy, such as projects from Google and Intel. In this thesis, the reader is introduced to a new project: the Fujitsu Project. The project is a collaboration between TU Delft and Fujitsu and has the goal of fabricating a new distributed quantum quantum computer based on color centers in diamond. The focus of the thesis is the definition of the microarchitecture.

The quantum computer stack is explained in detail. Precise and robust definitions for each of the seven layers of the quantum computer stack are given, where the definition of the microarchitecure is most important. A microarchitecture is defined as the list of instructions of the lowest level before entering control electronics. To define the diamond microarchitecture, a set of goals have to be completed. Other architectures such as QuTech's QuMA and QuTech's Central Controller were identified and analyzed. Combined with the requirements of the overall diamond system architecture as defined by the project, a list of requirements for the microarchitecture is created. Using these requirements, a Quantum Instruction Set Architecture (QISA) and a microarchitecture are defined.

Based on the defined QISA and microarchitecture, a compiler is designed. The compiler is made in OpenQL. OpenQL is a framework for high-level quantum programming that targets different quantum computing platforms. The main task of the compiler is to translate high-level quantum algorithms, expressed in a high-level quantum programming language (C++/Python APIs), to quantum microcode. The quantum microcode consists of instructions that are defined in the microarchitecture.

The QISA, microarchitecture and compiler are verified against the requirements that are set at the beginning of their respective definition phases. The microarchitecture supports for all gates that are part of cQASM 1.0. In addition, it supports all diamond color center specific protocols and rules. The compiler supports all instructions from cQASM as well. Moreover, the compiler supports all standard (gate) instructions and diamond specific instructions through OpenQL's Python API.

The work is intended to be a solid baseline, where the future of the project can rely and improve upon. Possible improvements could be the adaption of the microarchitecture to the growth of the number of controlled qubits per controller, the parallelization of the microarchitecture instructions to improve instruction throughput, and alignment with the quantum network group. The compiler can also be improved with for example enhanced scheduling, differentiation between qubit types and an entanglement library. The next step in the design of the microarchitecture will be the design of a microarchitecture simulator, which takes the microcode as input and simulates the hardware architecture.

With the proliferating networks, resource allocation based on Quality of Service (QoS) constraints mapping has been one of the difficulties faced by Internet Service Providers (ISP). The advent of new technologies such as virtualization and cloud computing have enabled the users to access content from anywhere around the world. This results in a need for an efficient and fast resource allocation method based on demand acting on the network. Many researchers have developed various algorithms to address this issue. However, they have considered only flow-based network properties, while the contemporary networks communicate mostly through path-based communication using the shortest paths. Inverse shortest path algorithm (ISPA) is a graph-theory based heuristic developed to solve this network resource allocation problem which considers both flow-based communication properties through Effective resistance matrix and path-based communication properties through shortest path matrix. Nevertheless, ISPA is so far implemented only for unweighted graphs. This study aims at assessing the feasibility of ISPA for weighted graphs by understanding the nature of Inverse shortest path problem (ISPP) bounds in weighted random graphs and implementing ISPA for weighted graphs. ISPP bounds behaviour is studied for weighted graphs by analyses of Q-norm distributions, probability of failure distributions and hopcount distributions. A feasibility condition verifying ISPP bounds is derived in relation with the input parameters of the weighted random graph. The solutions obtained through hop count distribution analysis are observed to be Poissonian in nature. Finally, ISPA is implemented for weighted graphs such that demand matrix can be resolved into a simple distance matrix to obtain solution which is a non-negative weighted Adjacency matrix and feasibility conditions are verified for the solutions obtained through ISPA.