This thesis provides an investigation of the architecture and the design of the coarse DACs in continuous time pipeline (CTP) ADC to achieve high SFDR performance within a large bandwidth at sampling frequency of 4.8 GHz in TSMC 28nm technology.
Mismatch errors of the coarse DACs in CTP ADC are very critical as they introduce distortion and leak the quantization noise of the coarse stages to the output. Conventional calibration techniques such as dynamic element matching (DEM) linearize the DACs by converting the DAC distortion to white noise. However, after the linearization, the residual gain errors of the DACs remain. As a result, the quantization noise of the coarse quantizers leak to the output and degrade the performance of the CTP. Therefore, the residual gain errors of the DACs need to be estimated and calibrated. A resistive DAC architecture is proposed in the first stage of the CTP. The proposed architecture employs conventional DEM technique and is verified within the first stage of the CTP. 
Furthermore, two new innovative techniques are presented in this thesis. The first technique, advanced dynamic element matching (ADEM), translates both the distortion and the gain errors due to element mismatch of the DACs in multi-stage CTP ADC into white noise. The second technique, advanced data weighted averaging (ADWA), noise shapes both the the distortion and the gain errors of the DACs. Therefore, the presented techniques do not require additional digital calibration for element mismatch errors. Finally, a DAC architecture is presented that allows a feasible implementation of the presented techniques. The techniques are verified using simulations in MATLAB and Cadence. However, The presented techniques require the CTP stages to have equal impedances. ... Read more

In this work, a SPAD-based LiDAR system is studied. In particular, the system employs a direct time-of-flight (dToF) method to reconstruct a target-reflected pulses using histogram, from which the distance to the target is estimated. More particularly, a time correlated single photon counting (TCSPC) method has been used to record the flight time of pulses. Such method assumes and successfully reconstructs the returned pulses in a photon starved condition, but fails under strong background noise. The increase in average photon counts per detection range limits the detection range, thereby rendering the system impractical for an automotive application where strong sunlight is present. The techniques proposed in this work, namely the asynchronous gating technique and the adaptive TDC gating technique, have been simulated for the SPAD-based LiDAR system and achieves a reliable detection range of 74m and reduces the required memory size by at least a factor of 14 in comparison to the system without a data compression technique, respectively.

In-pixel time-to-digital (TDC) converters are further studied in this work. In doing so, a novel Figure-of-Merits (FoM) is proposed, which illustrates a logarithmic relation between the proposed FoM and the technology node and that the ring oscillator architecture achieves a small form factor. Accordingly, a ring oscillator architecture is studied with various delay cell topologies, which are simulated and compared against each other. The stacked-inverter topology, biased by current sources, consumes the lowest power and suceptibilty to supply variation, while exhibiting comparable supply sensitivity and jitter with respect to compared topologies. It is therefore concluded that the stacked-inverter topology shall be considered as a delay cell topology when designing a ring oscillator based large array of in-pixel TDCs.
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To be able to cope with the demands of next generation radar applications, a bandwidth of 400MHz is required. The SAR assisted CT ∆Σ ADC provides an energy efficient ADC, but needs improvements to cope with the bandwidth enlargement. This thesis examines the front end components and thus initially focuses on resolving the issues in the front end. Although bandwidth enlargement is possible, the APF limits the performance resulting in an inefficient two-stage architecture. For optimal system efficiency, the APF requirements must be relaxed, which is achieved by decreasing the amount of resolved bits in the coarse ADC. Due to this reduction in bits, more stages must be incorporated into the architecture. To facilitate this, power and error budgets are devised to visualize the effects of adding stages. Hereafter, the 2 bit coarse ADC is compared to a 3 bit coarse ADC. This results in a trade-off
between the applicable gain (APF complexity) and the noise requirements of the front end.
The five-stage (2-2-2-2-6 bit) architecture proves to be the most promising design to achieve the desired FoMs of 172dB. Finally, in an attempt to optimize power efficiency, the APF and LPF filter are revised. The open loop filter implementation is compared to a closed loop filter implementation. It shows
that the open loop implementation exhibits very good power efficiency, but lacks in its linearity.
The closed loop implementation achieves the requirements, but consumes a lot of power. To optimize power consumption, the first and second stage must be implemented with the closed loop filters, but the third and fourth stage must be implemented with the open loop filters. ... Read more

The ΔΣ analog-to-digital converter (ADC) is widely used in audio applications for its high resolution. However, it is less energy efficient compared to Nyquist Rate ADCs. The growing demand for portable and wearable devices poses a more stringent power-efficient requirement on the audio system, and the traditional ADCs architecture is hard to achieve both high linearity and high energy efficiency. Zoom ADC is a proven energy-efficient hybrid structure for high-resolution and high-linearity applications. It consists of a front-end successive approximation register (SAR) ADC as a coarse stage and ΔΣ modulator backend to take advantage of the energy efficiency of a SAR ADC and the high resolution of a ΔΣ. However, the conventional zoom ADC suffers from distortion due to the input-correlated quantization error from the coarse stage. The tonal behavior (also known as “fuzz”) degrades overall linearity. This thesis describes a low cost, calibration-free method to suppress the fuzz in the zoom ADC. It improves the SNDR by introducing a 1st order fully passive noise shaper with a dithering to the coarse SAR ADC, which reduces the correlation of its quantization error with the input. A prototype ADC has been implemented in standard 160 nm CMOS process. It achieves 104.4dB peak SNR, 103.8 dB SNDR and 106.5 dB dynamic range (DR) in the audio band (20Hz~20kHz) at an oversampling ratio (OSR) of 62.5. The ADC consumes 317 μW from a 1.8V supply, thus resulting in a Schreier FoM of 185 dB. ... Read more

Analog-to-digital converters are important blocks in any electronic system which act as a bridge between analog signals and digital processors. The conventional SAR ADC employs a binary search algorithm and has emerged as the most suitable solution for low-power applications, due to its excellent power efficiency. The proposed ADC architecture incorporates a new design approach which combines the high resolution capabilities of oversampled ADCs with a 5-bit configuration asynchronous SAR ADC. In this thesis, the theory, analysis and design of a 2nd order error feedback noise shaping SAR are addressed. The underlying concept of the error feedback topology is to optimize the location of complex zeros in the noise transfer function and improve the SQNR for a lower sampling frequency. The stringent power and area budget imposes challenges in designing active blocks with a low transistor count. The impact of a new switching scheme for the capacitive DAC is examined analytically while considering the trade-off between linearity and power savings. The design uses a small assisting SAR and reaches 96% improvement in power consumption due to switching when comparing to a conventional scheme. The converter operates at 1 MHz and consumes 11 $\mu$W, from a 1.8 V supply. In a bandwidth of 20 kHz and an OSR of 25, it achieves an SNDR of 71 dB, an ENOB of 11.5 bits and a Walden FOM of 98 fJ/conversion-step. ... Read more

This thesis presents the design and implementation of a low power 3rd-order loop filter and a low power, compact, high-speed inverter-based amplifier designed in 28nm HPC for a GHz sampling Σ∆ modulator.
In the earlier design, the size of the pMOS in an inverter was found to be nine times larger than the nMOS which is not practical to obtain a compact design.
The proposed 4by4 inverter structure in a kind of matrix form achieves a gain of minimum 25dB and maximum 28dB at the worst corner and best corner without loading resistor respectively. The designed inverter amplifier is found to be relatively tolerant over PVT without an LDO. The simulation of the modulator system is implemented with an ideal quantizer and resistive DAC. The simulation results of the modulator shown an ENOB of 10bits with 0.41mW power consumption in the worst case and an ENOB of 10.7bits with 0.53mW power consumption in the best case.
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