This thesis focusses on improving the power efficiency of the front-ends used in wideband Continuous-Time Delta-Sigma Modulators (CTDSMs) (>100 MHz) with ultra-high linearity (<-100 dBc). The proposed front-end employs a passive RC Low-pass Filter (LPF) to suppress the high-frequency quantization noise at the output of the modulator’s feedback Digital-to-Analog Converter (DAC), thereby reducing the input swing in the front-end. The output of the LPF and the input signal are then summed by a low-noise Capacitively Coupled Instrumentation Amplifier (CCIA). This is followed by a pole-zero compensator, which ensures that the overall front-end behaves like an integrator. Simulations in a TSMC 28nm CMOS process indicate that a 5th-order CTDSM based on the proposed front-end will achieve better than -100 dBc THD and IM3, a peak SNDR of 74.1 dB over a 100 MHz bandwidth, while consuming only 45.4 mW of power. This is some 10% lower than that of prior work, and corresponds to a 167.5 dB Schreier Figure of Merit (FoM_S).

A continuous-time pipeline (CTP) analog-to-digital converter (ADC) consists of a number of cascaded stages, each employing a coarse ADC to digitize the residue signal generated by the previous stage. Compared to a continuous-time sigma-delta ADC, a CTP-ADC offers high bandwidth with relatively low sampling rates.

Due to the image signals produced by the coarse ADC, CTP-ADCs are easily saturated by input signals near integer multiples of the sampling frequency (k·Fs). In addition, the amplitude of the residue signal at the output of their first stages is sensitive to process variation. In this work, the delay line, employed to match the phase shift between different paths of a CTP-ADC, is a second-order all-pass filter (APF), while the coarse ADC is a first-order continuous-time sigma-delta modulator (CTMOD1). Together, these techniques improve near-Fs residue suppression by at least 6 dB and in-band residue suppression by 3.5 dB.

A transistor-level implementation of the CTMOD1 was made in 28nm CMOS. It consists of a 4-bit resistive DAC (RDAC), a 4-bit quantizer, and an active-RC integrator. It achieves 27 dB SNDR, -53 dB SFDR, and consumes 3.3 mW. Compared to an earlier coarse ADC design, which required 4-bit dither to mitigate in-band spurs, it requires only 1-bit dither.

Wireless data traffic is projected to steadily increase in the near future, necessitating the demand for transceivers with higher linearity and efficiency. Digital power amplifiers have the potential to achieve these higher efficiency demands while digital pre-distortion can be used to improve their linearity. Digital pre-distortion requires a highly-linear wideband observation receiver to down-convert and monitor the output of the transmitter. An observation receiver architecture that relies on baseband error-detection has been previously proposed by ELCA to reduce the stringent requirements on the analog-to-digital converter (ADC) in such an observation receiver. This thesis work presents a novel extremely-linear wideband voltage-domain harmonic-reject mixer targeting these observation receiver applications. The choice for a voltage-domain mixer instead of a current-domain mixer is first discussed. Three novel voltage-domain mixer topologies are then evaluated for their advantages and disadvantages, yielding the preferred topology for implementation. This circuit was designed in TSMC40nm thin-oxide CMOS technology yielding promising performance metrics when compared to similar state-of-the-art publications in the open literature; specifically in domain of observation receiver applications.

Quantum computing offers exponential speed-up for problems that are computationally intractable with classical computing. However, quantum processors with thousands to millions of quantum bits (qubits) are needed. Room-temperature electronics are used to control and readout today's qubits operating at cryogenic temperature. As the number of wires that can be placed between room temperature and the cryogenic chamber is limited, this creates a bottleneck in the scaling of quantum computers. Cryogenic CMOS (cryo-CMOS) electronics has been proposed to overcome this bottleneck. Operating the control electronics at cryogenic temperature, very close to the qubit, and controlling and reading out the qubits by frequency multiplexing relaxes the interconnect bottleneck. This work tackles this challenge by focusing on the qubit readout system and more specifically on the spin-qubit readout. The main target is to develop a cryo-CMOS analog-to-digital converter (ADC) for such an application. 
The readout of frequency multiplexed spin-qubits using RF reflectometry is considered the target application. The non-idealities of the RF-reflectometry scheme are simulated and analyzed for the qubit multiplexing and included in the system-level modeling of the readout chain. The target design specifications of the ADC are derived from such system-level simulations, resulting in the need for a 1 GSa/s ADC with ENOB > 6 bits operating at 4 K for the readout ~20 frequency-multiplexed spin-qubits with a BER of 1e-03.
Based on those specifications, this work proposes a 2-channel time-interleaved ADC using a Loop-Unrolled Successive Approximation Register (LU-SAR) ADC. The loop unrolling technique in combination with time-interleaving achieves the sampling rate of 1.1 GSa/s. The design includes the integration of a dynamic amplifier as an input driver and the generation of all required timing for the ADC core and the dynamic amplifier. Foreground calibration of the SAR comparator offset is included to achieve the linearity specifications. The ADC has been designed in TSMC 40nm CMOS technology and taped out for fabrication. After  calibration of comparator offset and calibration of the delay/gain mismatch between the two time-interleaved channels, the simulated performance of the ADC demonstrates an ENOB of 6.35 bits, SNDR of 40 dB, SFDR >50 dBc. The Figure-of-Merit of the designed ADC is 25.2 fJ/conv at 1 GSa/s sampling rate (including the driving amplifier and the clocking circuitry), which is significantly higher than the prior cryogenic ADCs and on-par with room-temperature state-of-the-art ADCs. The proposed ADC contributes towards the realization of future large-scale quantum computers, comprising million-qubit quantum processors integrated with cryogenic CMOS interface electronics.