The recent development of commercial phased array antennas for 5G at mm-wave frequencies (20 GHz to 60 GHz) introduces new challenges for radiation pattern characterization. Since these systems aim to employ active beamforming to steer the datastream to specific users, a single base station should be capable of deploying multiple beams simultaneously and electronically steer them to track the user. This introduces the need to characterize a large set of parameters and configurations.
As these modules become more cointegrated with the underlying transceiver chain, its internal modules are becoming less accessible and the device should be considered a unique black box for characterization purposes. Since the difficulty of sub-component testing increases, verifying antenna systems must be performed in an over-the-air (OTA) setup for the entire module.
Current antenna characterization utilizes a single probe, which relies on mechanical rotation to move the sensor around the antenna under test (AUT). This is a proven method, but typically takes several hours, depending on the required resolution. This becomes tedious and commercially unaffordable when multiple measurements are required. Furthermore, these systems require additional instruments, e.g. a vector network analyzer (VNA), which significantly increases the cost of the setups.
The concept proposed in this work avoids these drawbacks. It employs a large number of fixed sensing elements, enabling real-time radiation pattern acquisition. This has the potential to significantly reduce measurement time of 5G antenna systems. A key factor is the sampling of the signal right at the antenna probe, in contrast to the expensive VNA commonly used. This results in a lower complexity and cost, since there are significantly less high frequency components compared to other setups.
A prototype of this concept has been developed for two cross-sections of a dome, which provides real-time antenna pattern tracking capabilities. The high level of flexibility allows easy adaptation to different antenna systems. The sensing probes provide direct downconversion at the antenna, eliminating the need for a VNA. Furthermore, an algorithm is made that calculates the required number of sensor nodes depending on the antenna system under test. The high speed, modularity and low cost allow this setup to be an effective option for instantaneous verification of beam-steer capable antenna systems in the development and fabrication. This can ease the predicted antenna measurement bottleneck expected for the broad employment of small-cell 5G networks. The concept can be expanded to include features such as jammer injection and instantaneous error vector magnitude (EVM) measurement.

This thesis introduces the concept of phase rotation cancellation (PRC) as a previously unknown error mechanism in narrow-band FSK systems, and proposes a new FSK demodulation algorithm to resolve PRC errors. Phase rotation cancellation is defined as an event where the signal phasor rotation in the IQ plane is temporarily cancelled by the rotation of quadrature noise. The PRC errors are the dominant error mechanism in narrow-band FSK due to the small dynamic range at the output of a conventional FSK demodulator. In addition, any pre-modulation filtering further reduces the dynamic range and increases the probability for PRC errors to occur. Based on the discovered characteristics of PRC errors, a novel FSK demodulation algorithm is developed that greatly improves detection accuracy in FSK systems. Furthermore, the novel demodulation algorithm allows for sub-datarate receiver bandwidth operation, which offers improved receiver sensitivity and blocker performance. It is shown that the new demodulation algorithm eliminates nearly all PRC errors, leaving only errors due to clicks. In a GFSK system with BT = 0.5 and h = 0.5, an improvement in receiver sensitivity of up to 4.4 dB is achieved with the new demodulation algorithm.

A phase-domain analog-to-digital converter (PhADC) is a promising alternative to a pair of amplitude-domain in-phase and quadrature (IQ) ADCs for low power FSK/PSK demodulation, but due to the nonlinear amplitude-to-phase conversion, IQ offsets and gain mismatch can produce nonlinear phase distortions which that can lead to phase errors and an increase in bit-error rate (BER).
An IQ offset and gain mismatch detection technique is developed for PhADCs and verified. The offset and gain mismatch is estimated by detecting the phase vector distribution imbalance among the four phase quadrants after the analog-to-phase conversion. A feedback path has been constructed between the PhADC output and the offset/mismatch compensation interface. The closed loop will help the compensation interface to settle to the proper compensation values of the offset and mismatch. Incorporating this cancellation loop in a receiver system can improve its sensitivity and robustness.
In a conventional IQ ADC receiver we have two quantizations, i.e., one for I and one for Q, and then process the information to extract the phase. By contrast, the PhADC, due to its embedded demodulation attribute, performs only phase quantization. So only one quantization is needed. Because of its compactness, the hardware is simpler and thereby consumes less energy. Moreover the PhADC is immune to magnitude variations, because in an IQ ADC, amplitude quantization noise produces larger phase quantization noise at small vector
magnitudes, while in a PhADC a larger vector has the same phase quantization error as a small vector. Because of these advantages the PhADC is a very good candidate for low power communication. A detection algorithm has been developed that detects the phase vector distribution imbalance between the left and right IQ complex half plane in case of I offset and between the top and bottom of IQ complex half plane in case of Q offset. Using this imbalance we can determine the sign and size of IQ offset. A similar approach has been done for IQ gain mismatch, where the phase vector distribution imbalance is detected between the four phase quadrants in the IQ complex plane. A mixed-signal approach, i.e., detecting the offset and mismatch in the digital domain and compensate in the analog domain.
It is well known that in the IQ ADC receiver the offset and mismatch can be detected and calibrated if necessary before the amplitude is converted into phase in the digital domain, but in the PhADC receiver the offset and mismatch cannot be determined directly due to the absence of amplitude information. Here, we use phase information rather than amplitude information for detection and compensation. For this reason, we have created a direct mismatch and offset detection technique using the output phase signal of the PhADC. The relation between signal-to-noise power ratio (SNR) and its digital counter parts bit-energy-to-noise density (E_b/N_o) and symbol-energy-to-noise density (E_s/N_o) is established and is used to show the effect of IQ offset and gain mismatch on the BER as a function of channel and phase quantization noise from the PhADC.
It is shown that E_b/N_o and or E_s/N_o are not the same as SNR and less understood ratios that are often confused with SNR. The relation between SNR and Eb/No, or for higher dimensions (i.e., multiple bits per symbol), the E_s/N_o depends on the modulation parameters. For π/4 DQPSK modulation, the following relationship holds:E_b/N_o = SNR + 0.97 dB.
An ideal PhADC receiver for π/4 DQPSK demodulation, with a noise-free channel, can tolerate a maximum IQ offset of 28 mV and a gain mismatch of ± 25 dB for a required BER of 10^-5 according to the IEEE802.15.6 standard. But with a channel noise of SNR= 21dB these become 22 mV and ± 6 dB, respectively. A practical PhADC receiver with the same channel noise can tolerate a maximum IQ offset of 14mV and a gain mismatch of ± 3 dB.
An approach is presented to convert the PhADC receiver analog channel select filter to a digital one for discrete modeling purposes in Matlab Simulink. First, the Laplace transfer functions of the filter stages and from those the overall Laplace transfer function of the total filter are derived. A mapping procedure is proposed to convert the continuous time domain Laplace transfer function to a discrete one.

Recent years have seen an exponential growth in required wireless data capacity. This exponential growth is expected to continue, while it is unsustainable if the power consumption associated with it will grow at the same rate. This calls for better power efficiency, which can usually be found in polar power amplifier architectures. This thesis focuses on the feasibility of a power RF-DAC, with as main focus to seek improvement in power efficiency. As all information up to the RF output is in the digital domain the design will be frequency agile, meaning that operation frequency is only dependent on the external matching network.
As starting point an existing LDMOS technology is considered to implement a power Digital-to-RF-Amplitude Converter (DRAC) with a dedicated CMOS driver. As first demonstrator these two chips could be connected using flip-chip bonding. The proposed combination allows a maximum operation frequency of 3 GHz, providing a peak fundamental output power of 16,6 W with a drain efficiency of 64,4 % at the maximum operation frequency. Since the CMOS driver operates in Class-D a significantly lower average driver power consumption is expected compared to an analog system where a Class-A or Class-AB predriver would be used. This promising concept can change the way how future transmitters could be constructed. In conclusion a performance outlook will be given if a dedicated high power silicon technology that can feature the CMOS drivers would be available for 4G/5G applications.