8 records found
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Testing for Parasitic Memory Effect in SRAMs
Analysis and Test Development for Parasitic Fails in Deep Sub-Micron Memory Devices
Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs
Detecting memory faults in the presence of bit line coupling in SRAM devices
Bit line coupling memory tests for single cell fails in SRAMs
Parasitic memory effect in CMOS SRaMs
Worst-case bit line coupling backgrounds for open defects in SRAM cells
On-chip scratchpad memory size prediction and allocation for multiprocess embedded applications
