We demonstrate a 36 × 36 gate electrode crossbar that supports 648 narrow-channel field effect transistors (FET) for gate-defined quantum dots, with a quadratic increase in quantum dot count upon a linear increase in control lines. The crossbar is fabricated on an industrial ²⁸Si-MOS stack and shows 100% FET yield at cryogenic temperature. We observe a decreasing threshold voltage for wider channel devices and obtain a normal distribution of pinch-off voltages for nominally identical tunnel barriers probed over 1296 gate crossings. Macroscopically across the crossbar, we measure an average pinch-off of 1.17 V with a standard deviation of 46.8 mV, while local differences within each unit cell indicate a standard deviation of 23.1 mV. These disorder potential landscape variations translate to 1.2 and 0.6 times the measured quantum dot charging energy, respectively. Such metrics provide means for material and device optimization and serve as guidelines in the design of large-scale architectures for fault-tolerant semiconductor-based quantum computing.

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Quantum computing is on the verge of a transition from fundamental research to practical applications. Yet, to make the step to large-scale quantum computation, an extensible qubit system has to be developed. In classical semiconductor technology, this was made possible by the invention of the integrated circuit, which allowed to interconnect large numbers of components without having to solder to each and every one of them. Similarly, we expect that the scaling of interconnections and control lines with the number of qubits will be a central bottleneck in creating large-scale quantum technology. Here, we define the quantum Rent exponent p to quantify the progress in overcoming this challenge at different levels throughout the quantum computing stack. We further discuss the concept of quantum extensibility as an indicator of a platform's potential to reach the large quantum volume needed for universal quantum computing and review extensibility limits faced by different qubit implementations on the way towards truly large-scale qubit systems.

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We investigate the magnetic field and temperature dependence of the single-electron spin lifetime in silicon quantum dots and find a lifetime of 2.8 ms at a temperature of 1.1 K. We develop a model based on spin-valley mixing and find that Johnson noise and two-phonon processes limit relaxation at low and high temperature, respectively. We also investigate the effect of temperature on charge noise and find a linear dependence up to 4 K. These results contribute to the understanding of relaxation in silicon quantum dots and are promising for qubit operation at elevated temperatures.

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Semiconductor spins are one of the few qubit realizations that remain a serious candidate for the implementation of large-scale quantum circuits. Excellent scalability is often argued for spin qubits defined by lithography and controlled via electrical signals, based on the success of conventional semiconductor integrated circuits. However, the wiring and interconnect requirements for quantum circuits are completely different from those for classical circuits, as individual direct current, pulsed and in some cases microwave control signals need to be routed from external sources to every qubit. This is further complicated by the requirement that these spin qubits currently operate at temperatures below 100 mK. Here, we review several strategies that are considered to address this crucial challenge in scaling quantum circuits based on electron spin qubits. Key assets of spin qubits include the potential to operate at 1 to 4 K, the high density of quantum dots or donors combined with possibilities to space them apart as needed, the extremely long-spin coherence times, and the rich options for integration with classical electronics based on the same technology.@en