DC-to-DC converters have been used in portable electronic applications such as laptops and mobile phones where power efficiency is very important. In these applications, basic converters like buck and boost converters are used. However, the conversion ratio of conventional boost converters is not high. To achieve a high conversion ratio, the duty cycle of the conventional boost converters must be increased drastically, which increases the conduction loss. This thesis presents a topology to tackle this issue. A control system is designed and the pulse frequency modulation (PFM) method is used. In this thesis, a complete analysis of this topology, such as efficiency evaluation and stability analysis, is provided. This circuit is designed in 180nm BCD technology. Simulation results show it has a wide load range (0 to1.8A), high line regulation 0.8%/V, load regulation 2.9%/A, while achieving 88.1%, 93.0%, and 94.8% when CR = 5, CR = 4.5, and CR = 3.7, at <\ba= 1.2A respectively.

Class D amplifiers (CDA) have been used considerably in audio applications due to their high-efficiency behavior. Compared to standalone analog input CDAs, digital input CDAs are less sensitive to electromagnetic interference (EMI), which is preferred in automotive applications. For digital input CDAs, multi-bit current-steering DACs using tri-level units offer high dynamic range (DR) compared with other types of DAC. The main challenge in designing low total harmonic distortion plus noise (THD+N) and high DR IDAC lies in noise, mismatch, and ISI reduction. In this project, a new ISI resilient dynamic element matching technique is developed for mismatch shaping and ISI reduction in IDAC.

Class-D amplifiers have gained popularity for their high-power efficiency, exceeding 90%. Among them, digital-input Class-D amplifiers stand out due to their superior integration and increased immunity to electromagnetic interference (EMI). This project introduces a high-performance digital-input Class-D amplifier, aiming for a dynamic range larger than 130 dB while maintaining total harmonic distortion (THD) at approximately -110 dB.

It employs a capacitive digital-to-analog converter (CDAC) to minimize noise. Mismatch in the CDAC is addressed through mismatch shaping techniques. Additionally, an open-loop transconductance stage is incorporated into the loop filter, enhancing dynamic range and striving for optimal performance. Extra paths are introduced in the loop filter to guarantee that amplifier swings are maintained within the designated range.

GaN transistors have advantages over conventional Si MOSFETs, such as lower on-resistance, lower parasitic capacitance, higher break-down voltage, etc. However, due to the lack of the body diode, when GaN transistors conduct reverse current during dead time, the source-drain voltage (VSD) can be very large (up to 4-5 V, depending on the output current). High reverse conduction voltage leads to large power loss during dead time for the GaN class D amplifier. In this project, a dead time control circuit is proposed. With the dead time control circuit, the dead time can be reduced from a large default value to around 5 ns. The output power of the class D amplifier can be improved, and the third-order harmonic distortion can also be improved by 5-10 dB for different corners and temperatures.

Class-D amplifiers are quickly becoming the standard in many audio applications. Their highly efficient behavior and wide power range make these amplifiers more suitable than traditional Class A/AB audio amplifiers. Battery-powered devices are a particularly interesting sub-field due to their special demand for extended battery duration and higher efficiency. An output power lower than 2 W, along with good performances in terms of linearity and efficiency, is often required. Many stand-alone Class-D Amplifiers have analog inputs, making them susceptible to interference that negatively impacts their behavior. This problem can be mitigated by employing an insensitive input digital interface. Many standard solutions often require complex architectures, which limit these systems' reliability. This work proposes a digital-input class-D amplifier with a multi-level output stage that, together with a relatively low (480 kHz) switching frequency, reduces idle power consumption while achieving good linearity. Based on a 180 nm BCD technology, it can drive a 16-Ω load showing pre-layout simulated performances: -111.3 dB THD+N, 115.6 DR, 91.4 % peak efficiency, and 2.14 mW idle power consumption.