In chopper amplifiers, the interaction between the input signal and the chopper clock can cause intermodulation distortion (IMD). This is mainly due to finite amplifier bandwidth, which causes signal-dependent output spikes at the chopping transitions. Such chopper-induced IMD can be mitigated by the fill-in technique, which involves ping-ponging between the outputs of two identical OTAs chopped in quadrature, thus generating a spike-free output. In this letter, a relaxed implementation is proposed in which the output of a fill-in OTA is only briefly used to avoid the spikes of a chopped main OTA. As a result, the fill-in OTA does not need to be chopped, and so it can be duty-cycled to save power. Furthermore, the chopper ripple caused by the main OTA can now be suppressed by a single low-noise ripple-reduction loop, rather than the two AZ loops required in a previous ping-pong implementation of the fill-in technique. Compared to the latter, the proposed amplifier achieves similar IMD performance (-125.7 dB), a 25× lower input current (22.6 pA), and a flat noise floor (12 nV/ Hz).

This article describes an auto-zero stabilized voltage buffer that achieves low offset and low noise with sub-pA input current. A high gain stabilization loop is used to periodically cancel the buffer’s offset. The loop itself is periodically disconnected from the buffer and auto-zeroed, during which its bandwidth is reduced to reduce the associated noise folding. However, this also reduces its offset correction range, and so to avoid overloading, its initial offset is digitally trimmed. To break up the correlation between the residual low-frequency (LF) noise of the auto-zero and stabilization phases, the loop is periodically chopped, which significantly reduces the buffer’s LF noise. Finally, the duty-cycle of the two phases is optimized to bring the buffer’s LF noise density close to 2–√ times its white noise density (14 nV/ Hz−−−√ ), which is the fundamental limit of an AZ amplifier. The buffer also achieves a constant and low input current (0.8 pA), as well as a state-of-the-art offset (0.4 μV ).

The readout of high-impedance sensors and sampled voltage references [1] requires amplifiers that can achieve both low offset and low input current. Recently, it has been shown that this unique combination can be achieved by an auto-zero (AZ) stabilized buffer [2]. However, its low-frequency noise density is surd 5 times higher than the buffer's own white-noise voltage spectral density e _n . Furthermore, its input current is not constant, but varies significantly with the input voltage. To overcome the first issue, a chopped AZ stabilization loop with an optimized duty-cycle is proposed to bring the low-frequency noise density close to surd 2cdot {e}-{n}, the fundamental limit of an AZ stabilized amplifier. The second issue is solved by replacing the transmission-gate input switches used in [2] with NMOS switches and a constant Vgs drive. This keeps their charge injection constant over a wide input voltage range, and results in a constant input current.

This paper presents a class-AB driver for high-fidelity audio. It attains high-linearity at low-power by using an improved output stage biasing technique and a new frequency compensation scheme. Designed in standard 65nm CMOS, the driver delivers 5I.2mW peak power to 16Ω 0.33nF load, while consuming 0.97mW. It achieves -101.4dB THD+N over full audio band, the lowest ever reported linearity among sub-milliwatt CMOS class-AB drivers. Compared to prior works, it has >12dB better linearity and >7x higher unity-gain bandwidth, resulting in 2.5x improvement in linearity FOM (=Peak Load Power/ (Quiescent Power × THD+N[%])).