This article presents a low-noise transimpedance amplifier (TIA) designed for miniature ultrasound probes. It provides continuously variable gain to compensate for the time-dependent attenuation of the received echo signal. This time-gain compensation (TGC) compresses the echo-signal dynamic range (DR) while avoiding imaging artifacts associated with discrete gain steps. Embedding the TGC function in the TIA reduces the output DR, saving power compared to prior solutions that apply TGC after the low-noise amplifier. The TIA employs a capacitive ladder feedback network and a current-steering circuit to obtain a linear-in-dB gain range of 37 dB. A variable-gain loop amplifier based on current-reuse stages maintains constant bandwidth in a power-efficient manner. The TIA has been integrated in a 64-channel ultrasound transceiver application-specific integrated circuit (ASIC) in a 180-nm BCDMOS process and occupies a die area of 0.12 mm2. It achieves a gain error below ±1 dB and a 1.7 pA/ √ Hz noise floor and consumes 5.2 mW from a ±0.9 V supply. B-mode images of a tissue-mimicking phantom are presented that show the benefits of the TGC scheme.

This article presents a fully integrated 64-channel programmable ultrasound transmit beamformer for catheter-based ultrasound probes, designed to interface with a capacitive micro-machined ultrasound transducer (CMUT) array. The chip is equipped with programmable high-voltage (HV) pulsers that can generate ±30-V return-to-zero (RZ) and non-RZ pulses. The pulsers employ a compact back-to-back isolating HV switch topology that employs HV floating-gate drivers with only one HV MOS transistor each. Further die-size reduction is achieved by using the RZ switches also as the transmit/receive (T/R) needed to pass received echo signals to low-voltage receive circuitry. On-chip digital logic clocked at 200 MHz allows the pulse timing to be programmed with a resolution of 5 ns, while supporting pulses of 1 cycle up to 63 cycles. The chip has been implemented in 0.18-μm HV Bipolar-CMOS-DMOS (BCD) technology and occupies an area of 1.8 mm ×16.5 mm, suitable for integration into an 8-F catheter. Each pulser with embedded T/R switch and digital logic occupies only 0.167 mm2. The pulser successfully drives an 18-pF transducer capacitance at pulse frequencies up to 9 MHz. The T/R switch has a measured ON-resistance of ~180Ω. The acoustic results obtained in combination with a 7.5-MHz 64-element CMUT array demonstrate the ability to generate steered and focused acoustic beams.

Miniature ultrasound probes, such as the intra-cardiac echography (ICE) probe shown in Fig. 23.6.1, increasingly employ in-probe ASICs to interface with the elements of an ultrasound transducer array to improve signal quality and reduce cable count [1]-[4]. For each transducer element, such an ASIC contains a pulser that drives the element to generate a pressure wave, a low-noise amplifier (LNA) that amplifies the resulting echo signal, and a time-gain compensation (TGC) circuit that compensates for the time-varying echo-signal amplitude due to propagation attenuation of the acoustic wave. Without TGC, the first echoes, from shallow tissue, are much larger than later echoes from deeper tissue. The TGC circuit corrects for this, ideally by providing a gain that increases exponentially with time, thus reducing the dynamic range (DR) by as much as 40dB and strongly relaxing the requirements of subsequent blocks. In conventional ultrasound systems, TGC is typically performed after the LNA, implying that a power-hungry LNA is required that can handle the full DR of the echo signal [5], [6]. In recent in-probe ASICs, programmable-gain LNAs have been employed that provide a step-wise TGC approximation [1]-[3]. While this saves power, the associated gain-switching transients lead to imaging artefacts. In this paper, we present an LNA with a built-in continuous TGC function that mitigates this problem. The LNA is a transimpedance amplifier (TIA) optimized to amplify the signal current of a capacitive micro-machined ultrasound transducer (CMUT). We demonstrate its integration into a 64-channel ASIC for a CMUT-based ICE probe.

Intravascular ultrasound is an imaging modality used to visualize atherosclerosis from within the inner lumen of human arteries. Complex lesions like chronic total occlusions require forward-looking intravascular ultrasound (FL-IVUS), instead of the conventional side-looking geometry. Volumetric imaging can be achieved with 2D array transducers, which present major challenges in reducing cable count and device integration. In this work we present an 80-element lead zirconium titanate (PZT) matrix ultrasound transducer for FL-IVUS imaging with a front-end application-specific integrated circuit (ASIC) requiring only 4 cables. After investigating optimal transducer designs we fabricated the matrix transducer consisting of 16 transmit (TX) and 64 receive (RX) elements arranged on top of an ASIC having an outer diameter of 1.5 mm and a central hole of 0.5 mm for a guidewire. We modeled the transducer using finite element analysis and compared the simulation results to the values obtained through acoustic measurements. The TX elements showed uniform behavior with a center frequency of 14 MHz, a -3 dB bandwidth of 44 % and a transmit sensitivity of 0.4 kPa/V at 6 mm. The RX elements showed center frequency and bandwidth similar to the TX elements, with an estimated receive sensitivity of 3.7 μV/Pa. We successfully acquired a 3D FL image of three spherical reflectors in water using delay-and-sum beamforming and the coherence factor method. Full synthetic aperture acquisition can be achieved with frame rates on the order of 100 Hz. The acoustic characterization and the initial imaging results show the potential of the proposed transducer to achieve 3D FL-IVUS imaging.

This paper presents an area- and power-efficient application-specified integrated circuit (ASIC) for 3-D forward-looking intravascular ultrasound imaging. The ASIC is intended to be mounted at the tip of a catheter, and has a circular active area with a diameter of 1.5 mm on the top of which a 2-D array of piezoelectric transducer elements is integrated. It requires only four micro-coaxial cables to interface 64 receive (RX) elements and 16 transmit (TX) elements with an imaging system. To do so, it routes high-voltage (HV) pulses generated by the system to selected TX elements using compact HV switch circuits, digitizes the resulting echo signal received by a selected RX element locally, and employs an energy-efficient load-modulation datalink to return the digitized echo signal to the system in a robust manner. A multi-functional command line provides the required sampling clock, configuration data, and supply voltage for the HV switches. The ASIC has been realized in a 0.18-μm HV CMOS technology and consumes only 9.1 mW. Electrical measurements show 28-V HV switching and RX digitization with a 16-MHz bandwidth and 53-dB dynamic range. Acoustical measurements demonstrate successful pulse transmission and reception. Finally, a 3-D ultrasound image of a three-needle phantom is generated to demonstrate the imaging capability.

This paper presents a front-end application-specified integrated circuit (ASIC) integrated with a 2-D PZT matrix transducer that enables in-probe digitization with acceptable power dissipation for the next-generation endoscopic and catheter-based 3-D ultrasound imaging systems. To achieve power-efficient massively parallel analog-to-digital conversion (ADC) in a 2-D array, a 10-bit 30 MS/s beamforming ADC that merges the subarray beamforming and digitization functions in the charge domain is proposed. It eliminates the need for costly intermediate buffers, thus significantly reducing both power consumption and silicon area. Self-calibrated charge references are implemented in each subarray to further optimize the system-level power efficiency. High-speed datalinks are employed in combination with the subarray beamforming scheme to realize a 36-fold channel-count reduction and an aggregate output data rate of 6 Gb/s for a prototype receive array of 24 x 6 elements. The ASIC achieves a record power efficiency of 0.91 mW/element during receive. Its functionality has been demonstrated in both electrical and acoustic imaging experiments.

This paper presents a front-end ASIC for forward-looking intravascular ultrasound (IVUS) imaging. The ASIC is intended to be mounted at the tip of a catheter and can interface a total of 80 piezo-electric transducer elements with an imaging systems using only 4 cables, thus significantly reducing the system complexity compared to the prior art. It is capable of switching high-voltage transmit pulses to 16 transmit elements, and capturing the resulting echo signals using 64 multiplexed receive elements. The ASIC digitizes the received signals locally, providing more robust communication than prior analog approaches. Measurements show that the ASIC effectively switches transmit pulses up to 30 V, and digitizes echo signals with a bandwidth of 16 MHz, while consuming only 10 mW. Acoustic measurements in combination with a prototype transducer array demonstrate pulse transmission and reception. Finally, a B-mode image of a needle phantom demonstrates the imaging capability.