S

SM Sinaga

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20 records found

Electromagnetic optimization of a wafer-level package for RF-MEMS applications

Shellcase-type wafer-level packaging solutions: RF characterization and modeling

Substrate crosstalk suppression using wafer-level packaging: metalized through-substrate trench approach
Doctoral thesis - SM Sinaga

Wafer-level packaging for rf applications using low-loss spacer substrate for integration of passives
Conference paper - SM Sinaga, A Poliakov, M. Bartek

Modeling and analysis of substrate coupling in silicon integrated circuits
Conference paper - SM Sinaga, M. Bartek, JN Burghartz

Circuit partitioning and RF isolation by through-substrate trenches
Conference paper - SM Sinaga, A Poliakov, M. Bartek, JN Burghartz

High-resistivity polycrystalline silicon as rf substrate in wafer-level packaging

Wafer-level packaging for RF applications using high-resistivity polycrystalline silicon substrate technology
Conference paper - A Poliakov, SM Sinaga, M. Bartek, JN Burghartz

Influence of via-connections on electrical performance of vertically-spaced rf passives
Conference paper - M. Bartek, SM Sinaga, JN Burghartz

On-chip rf isolation in stacked wafer-level packages
Conference paper - SM Sinaga, M. Bartek, JN Burghartz

Wafer-level chip-scale packaging for low-end RF products

Thermal effects in suspended RF spiral inductors

On-chip isolation in wafer-level chip-scale packages: substrate thinning and circuit partitioning by trenches
Conference paper - SM Sinaga, A Poliakov, M. Bartek, JN Burghartz

Study of thermal behaviour in a multi-chip-composed optoelectronic package
Conference paper - J. Tian, SM Sinaga, M. Bartek

Processability and electrical characteristic of glass substrates for RF wafer-level chip-scale packages

Substrate thinning and trenching as crosstalk suppression techniques
Conference paper - SM Sinaga, A Poliakov, M. Bartek, JN Burghartz

Characterization of high-resistivity polycrystalline silicon substrates for wafer-level packaging and integration of RF passives

Vertical integration of rf passive components in stacked wafer-level packages
Conference paper - M. Bartek, SM Sinaga, JN Burghartz

Wafer-level integration of on-chip antennas and RF passives using high-resistivity polysilicon substrate technology

Chip-level electromagnetic isolation
Report - SM Sinaga