Substrate crosstalk suppression using wafer-level packaging: metalized through-substrate trench approach

Study of thermal behaviour in a multi-chip-composed optoelectronic package

Parasitic effects reduction for wafer-level packaging of RF-MEMS

Electromagnetic optimization of a wafer-level package for RF-MEMS applications

RF crosstalk suppression based on wafer-level packaging concept

Influence of via-connections on electrical performance of vertically-spaced rf passives

Vertical integration of rf passive components in stacked wafer-level packages

High-resistivity polycrystalline silicon as rf substrate in wafer-level packaging

On-chip rf isolation in stacked wafer-level packages

Wafer-level packaging for rf applications using low-loss spacer substrate for integration of passives

Thermal effects in suspended RF spiral inductors

Wafer-level chip-scale packaging for low-end RF products

Shellcase-type wafer-level packaging solutions: RF characterization and modeling

Wafer-level packaging for RF applications using high-resistivity polycrystalline silicon substrate technology

Wafer-level integration of on-chip antennas and RF passives using high-resistivity polysilicon substrate technology

Characterization of high-resistivity polycrystalline silicon substrates for wafer-level packaging and integration of RF passives

Circuit partitioning and RF isolation by through-substrate trenches

Substrate thinning and trenching as crosstalk suppression techniques

On-chip isolation in wafer-level chip-scale packages: substrate thinning and circuit partitioning by trenches

Analysis and optimization of via-connected spiral inductors in RF silicon technology