49 records found
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MBIST architecture framework based on orthogonal constructs
New algorithms for address decoder delay faults and bit line imbalance faults
Defect oriented testing of the strap problem under process variations in DRAMs
Space of DRAM fault models and corresponding testing
Memory test experiment: industrial results and data
DRAM-specific space of memory tests
Opens and delay faults in CMOS RAM address decoder
Influence of bit line coupling and twisting on the faulty behavior of DRAMs
Impact of stresses on the fault coverage of memory tests
Framework for fault analysis and test generation in drams
Influence of bit line twisting on the faulty behavior or DRAMs
The state-of-art future trends in testing embedded memories
Detecting faults in peripheral circuits and an evaluation of SRAM tests
The effectiveness of Scan test and its new variants
Tests for address decoder delay faults in RAMs due to inter-gate opens
An industrial evaluation of DRAM tests
Soft faults and the importance of stresses in memory testing
Effects of bit line coupling on the faulty behavior of DRAMs
Linked faults in random access memories: concept fault models, test algorithms, and industrial results
Consequences of RAM bitline twisting for test coverage
