Av

AJ van de Goor

View Pure Profile

Authored

20 records found

Detecting faults in peripheral circuits and an evaluation of SRAM tests
Conference paper - AJ van de Goor, S. Hamdioui, R Wadsworth

Approximating infinite dynamic behavior for DRAM cell defects
Conference paper - Z. Al-Ars, AJ van de Goor

Modeling techniques and tests for partial faults in memory devices
Conference paper - Z. Al-Ars, AJ van de Goor

Dynamic faults in random-access-memories: concept, fault models and tests

March SL: a test for all static linked memory faults

Importance of dynamic faults for new SRAM technologies

Testing static and dynamic faults in random access memories
Conference paper - S. Hamdioui, Z. Al-Ars, AJ van de Goor

Memory test experiment: industrial results and data

Linked faults in random access memories: concept fault models, test algorithms, and industrial results

New algorithms for address decoder delay faults and bit line imbalance faults

Testing (embedded) memories: new fault models, test, DfT, BIST, BISR, and industrial results
Conference paper - AJ van de Goor

Memory testing
Book chapter - AJ van de Goor, N Jha, S Gupta

A systematic method for modifying march tests for bit-oriented memories into tests for word-oriented memories
Journal article - AJ van de Goor, IBS Tlili

A fault primitive based analysis of dynamic memory faults

Analyzing the impact of process variations on DRAM testing using border resistance traces
Conference paper - Z. Al-Ars, AJ van de Goor

An industrial evaluation of DRAM tests
Journal article - AJ van de Goor

DRAM-specific space of memory tests

Introduction
Book chapter - AJ van de Goor, N Jha, S Gupta

Effects of bit line coupling on the faulty behavior of DRAMs
Conference paper - Z. Al-Ars, S. Hamdioui, AJ van de Goor

Test point insertion that facilitates ATPG in reducing test time and data volume