In this thesis, we present a RISC-V processor that is extended with the MOLEN ISA extension, thereby granting it dynamic reconfiguration capabilities. The reconfigurable microcode (ρμ-code) of the MOLEN paradigm is modified to be suitable for (FPGA) implementation in the 64-bit Linux-capable CVA6 RISC-V processor. The set instruction performs reconfigurations by pointing it to a partial bitstream address, after which the execute instruction can perform operations on the reconfigured hardware. To this end, the concept of nested ρμ-code is presented, in which the reconfigurable opcodes are encapsulated in regular RISC-V instructions. Furthermore, a status instruction is introduced to enable the reconfiguration to be performed in the background. Consequently, the reconfiguration latency can be hidden, by allowing the CPU to do useful work during the reconfiguration. Using various experiments, it is demonstrated that the proposed implementation has a near-optimal reconfiguration performance and that the reconfiguration latency can be effectively hidden in typical cases.

Forensics is the art of gathering evidence, which for electronics amounts to accurately recovering data. Often, this can only be archived with state-of-the-art hacking techniques.
However, replicating state-of-the-art research in hardware security can be difficult, due to the large number of components and connections. To counter this, a custom Printed Circuit Board (PCB) is presented, that aids with hardware attacks, and allows them to be executed in a reliable and reproducible way.
The PCB is targeted specifically towards hardware encrypted USB drives, and provides accessible ways to break out and interact with the target’s electrical components.

In the first part of this thesis, the design and fabrication of the platform, called LUPIn, short for Lawful Unlocking of PIN-protected USB drives, is established. The design integrates commonly-used components and functions, making it suitable for a wide range of different attacks and devices. It also incorporates robust and traceable connections to the target.
In the second part, LUPIn is verified by implementing it in a real attack. The target is a PIN-protected USB drive, which contains an IC performing key derivation. Since the debug port is not fully secured, a technique called Cold-Boot Stepping is used. This method is specifically designed to circumvent partially disabled debug ports.
To analyse the gathered data, it first must be filtered. This filtering is done using a graph-based algorithm.
In one crytographic function, an input parameter is used twice with different XOR masks. By analyzing all the filtered data, it is possible to find masked values, and use those to recover the original input value.

Concluding, a hardware tooling PCB (LUPIn) is successfully designed, assembled and tested. It proves to be a reliable platform for performing hardware attacks against encrypted USB drives. It makes development of hardware attacks simpler and less time-consuming.
In the validation of LUPIN, a real-life USB drive is successfully attacked. Thousands of RAM snapshots are collected and an algorithm is developed to filter this data. A single variable can be extracted, but it ultimately proved insufficient to fully crack the target.

Nowadays, the society strongly depends on computer networks and systems as a means of reliable communication and data storage. In order to maintain absolute security of the networks and thus the society, one would need to separate everything, but this is not feasible. Consequently, sharing of resources is inevitable. There are security products that rely on an FPGA to create domain separation. The domain separation is required to prevent leakage of confidential information and manipulating of critical processes. A modern FPGA has enough resources to have multiple soft-cores initiated on it- each of them working in a different domain. However, due to the limited amount of IO pins on an FPGA, using multiple DRAM chips is not an option. Therefore a single DRAM is shared between multiple soft-cores, threatening the domain separation. The main threats when using a shared DRAM are communication channels due to latency deviations, data corruption due to rowhammering and direct access to unauthorized data due to the data being available on shared addresses. Research has been done to determine what causes the latency deviation and how to mitigate it. The results of the research are that the only fundamental solution to mitigate the latency deviation is to have a fixed latency when accessing the DRAM. A fixed time arbiter is designed and tested. The fixed time arbiter is using a deterministic delay after each DRAM access in order to mitigate the latency deviation. Before mitigating the rowhammer vulnerability it is shown that rowhammering causes bitflips not only in the adjacent rows, but also in non-adjacent rows. To mitigate the rowhammer vulnerability for adjacent rows, a row refresher is created that tracks the rows that are accessed and refreshes the adjacent rows when accessed more than the bitflip threshold. To mitigate the vulnerability for non adjacent rows a test is created to give an overview of all non adjacent rows that contain bitflips so that those rows can be be dedicated as unused guard rows. The last part that is implemented is an address mapper to be sure that no soft-core can access the addresses of another soft-core. The fixed time arbiter, row refresher and address mapper are combined into the memory domain protector. The consequence on the bandwidth of the DRAM is that the bandwidth is halved compared to the benchmark design. The memory domain protector also uses 23× more logic than a standard arbiter. 

Recent trends in machine learning (ML) have placed a strong emphasis on power- and resource-efficient neural networks, as well as the development of neural networks on edge devices. Spiking neural net-works (SNNs), due to their event-based nature, are one of the most promising types of neural networks for low-power applications. To accelerate and ease the deployment of SNNs on edge devices, this thesis presents a configurable digital neuromorphic hardware generator for heterogeneous computing that is capable of generating resource-efficient SNN processing cores. The proposed hardware generator is de-veloped using SpinalHDL, a high-level hardware description language (HDL), which provides a high level of flexibility in hardware generation. Our generator supports the configuration on various parameters and is capable of generating a tree-structured multi-core architecture of heterogeneous cores. The generator is deployed in a sensor-fusion hand-gesture classification use case, for which the configurability of our hardware generator is a key enabler.

Voice activity detection (VAD) is the prevailing approach to extracting meaningful speech information from the pervasive noise found in the physical environment. Presently, deep neural networks (DNN) are widely employed as the classifier component in Voice Activity Detection (VAD) systems. However, conventional deep neural networks, like fully connected (FC) deep neural networks, encounter the challenge of excessive computational complexity. This heightened complexity can result in diminished computing efficiency, unnecessary utilization of hardware resources, and redundant power consumption. To address the inefficiency issue from computational complexity, this study introduces a novel neural network architecture named DeltaFC. This architecture attains an operation time latency of less than 1 ms for each 30ms voice segment, resulting in a 54% reduction in latency compared to the baseline fully connected (FC) model. In software design, this study tackles the issue by compressing and encoding time-series information using the Delta algorithm, with the objective of introducing temporal sparsity. Based on the software results, the neural network surpasses both the baseline fully connected (FC) and LSTM models in AUC (area under the curve), with accuracy at a lightweight parameter scale. In hardware design, this study reproduces the neural network software design into FPGA hardware RTL design, implementing a lightweight digital IP core. This digital IP core accelerates neural network operations in hardware by the deployment of Delta and CSR algorithms. Compared with not introducing temporal sparsity, the computing efficiency increases by approximately 85% with 0.5% loss in accuracy. This substantiates that within the domain of lightweight neural networks containing fewer than 30,000 parameters, the DeltaFC network proposed in this study is more suitable for Voice Activity Detection (VAD) when compared to fully connected (FC), LSTM, and other baseline network architectures.

Tydi is an open specification for streaming dataflow designs in digital circuits, allowing designers to express how composite and variable-length data structures are transferred over streams using clear, data-centric types. This provides a higher-level method for defining interfaces between components as opposed to existing bit- and byte-based interface specifications.

In this thesis, an open-source intermediate representation (IR) is introduced which allows for the declaration of Tydi's types. The IR enables creating and connecting components with Tydi Streams as interfaces, called Streamlets. It also lets backends for synthesis and simulation retain high-level information, such as documentation. Types and Streamlets can be easily reused between multiple projects, and Tydi’s streams and type hierarchy can be used to define interface contracts, which aid collaboration when designing a larger system.

The IR codifies the rules and properties established in the Tydi specification and serves to complement computation-oriented hardware design tools with a data-centric view on interfaces. To support different backends and targets, the IR is focused on expressing interfaces, and complements behavior described by hardware description languages and other IRs. Additionally, a testing syntax for the verification of inputs and outputs against abstract streams of data, and for substituting interdependent components, is presented which allows for the specification of behavior.

To demonstrate this IR, a grammar, parser, and query system have been created, and paired with a backend targeting VHDL.

With the increase in the amount of data being gathered, the need for data processing is also rising. Furthermore, in addition to the proprietary ISAs that have been prevalent, the free and open RISC-V ISA has seen major interest. The modularity of the RISC-V ISA allows it to be extended with many instruction set extensions. One such extension that aids in the processing of large amounts of data is the P-extension, which introduces packed-SIMD instructions. In this thesis, the RISC-V based open-source CVA6 processor is extended to support the SIMD instructions defined by the P-extension. In order to do so, the 332 instructions of the P-extension are divided into subsets based on the type of instructions used by applications that make use of SIMD instructions and the hardware needed to implement those instructions. Due to time constraints 268, or 80.7%, of the total 332 instructions were implemented. However, this includes all the instructions that could be utilized by the used benchmarks. Therefore, the benchmark results show the full performance achievable by the P-extension. These 268 instructions make up the basic, MAC 8-bit, MAC 16-bit, and MAC 32-bit subsets. The ALU has been modified to operate in a SIMD manner on 8 8-bit, 4 16-bit, 2 32-bit, and 64-bit elements. Moreover, it has been extended to support new operations like data movement or reorganization instructions. Like the ALU, the multiplier has also been converted into a SIMD multiplier using a SIMD Baugh-Wooley scheme. Furthermore, the multiplier has been extended to also function as a MAC unit. The impact of these newly added SIMD instructions is tested in an ideal scenario of matrix multiplication as well as in a real-world machine learning application. In matrix multiplication, a speedup of up to 8.8x and 7.2x is seen for 8-bit and Q7 elements and 4.9x and 3.8x for 16-bit and Q15 elements when only using instructions from the basic subset. When also using the MAC instructions, the speedup increases to up to 12.3x and 12.6x for 8-bit and Q7 elements and 6.7x and 6.5x for 16-bit and Q15 elements. The real-world benchmark consists of an image recognition convolutional neural network based on the CIFAR-10 data set. In this benchmark, a speedup of 2.1x and 3.3x is obtained for respectively the basic subset and with MAC instructions. However, the additional hardware comes at a cost, specifically an increase of 5.0% LUT and 0.05% flip-flop usage for the basic subset or 7.2% increased LUT and 0.56% increased flip-flop usage with the basic and MAC subsets. While the additional hardware can have an impact on the maximum achievable clock frequency, the critical path remains in the FPU. The maximum achievable clock frequency is therefore not impacted and reaches 70 MHz on a Xilinx Kintex-7 FPGA.

Some server hosters facilitate cyber crime either intentionally (so called “bulletproof hosters”) or unintentionally (“bad hosters”). When dealing with uncooperative hosters during forensic investigations, it may sometimes be necessary to collect data or information on the servers without help from the owner of the server. Data within the RAM might prove insightful in, for example, determining active processes or reveal crypto graphically interesting information like encryption keys. The thesis explains key concepts within memory organization and the PCIe standard.Afterwards, it discusses several techniques for RAM acquisition and categorizes and evaluates them using a model-based approach. The thesis then dives deeper into DMA-based memory acquisition using PCIe and proposes several improvements to current DMA attacks in order to create a better memory acquisition technique. A novel memory acquisition technique is created by hot-plugging aPCIe device and skipping over the regular enumeration procedure. This techniqueal lows the memory acquisition to be executed without a reboot and provides a stealth approach to accessing the memory.  

Implantable Medical Devices (IMDs) are deployed in patients to treat a range of medical conditions. Technological advancements have enabled manufacturers to fit IMDs with specialized hardware that accelerates compute-intensive medical therapies next to a software-run host processor. However, mostly hardware acceleration is found in the form of ASIC peripherals next to a host processor in state-of-the-art IMDs, while low-power FPGAs could provide a comparable performance gain with the added benefit of the upgradability of functionality. Existing literature about low-power FPGAs focuses on new algorithms or performance improvements, while largely ignoring power and energy analysis, the latter being the most limiting factor in the IMD environment. This thesis investigates under what conditions FPGAs could be added to IMDs by developing two use cases: an FPGA securing wireless communication, and accelerating a neural network aiding medical therapies that depend on pattern detection. These cases are evaluated on FPGA, eFPGA and MCU with ASIC peripheral platforms, from which performance, energy usage and prospected IMD battery life is derived. On one end, it was found that AES encryption used 4.4 times the energy of an MCU hardware-accelerated implementation while being 17% slower. However, employing lightweight ciphers on the FPGA closes this gap. Furthermore, adding an FPGA results in only a 7.5% decrease in battery life when the FPGA is shut off during idling to combat its high static current draw. Running an FPGA-accelerated neural network is feasible if the active time is 6.5 minutes per day. With weekly recharging, continuous monitoring is possible. Using an eFPGA, which is an embedded FPGA fabric integrated within an MCU, results in using only 12% to 21% of the FPGA package area and is almost 2 times as energy efficient under 2 minutes daily usage as an FPGA. As FPGAs in IMDs is a novel field, research was done in legal regulation of IMDs, where it was found that existing regulations on software devices also applies to FPGAs. Therefore, all obstacles of the technical and legal kind have been removed that hold IMD manufacturers from using FPGAs in their devices.

Computation-In-Memory (CIM) employing Resistive-RAM
(RRAM)-based crossbar arrays is a promising solution to implement Neural Networks (NNs) on hardware, such that they are efficient with respect to consumption of energy, memory, computational resources, and computation time. In this respect, Binary NNs (BNNs), where the weights obtain single binary values, are inherently suitable for cost-effective CIM-based NN implementations. However, RRAM devices, due to variability and reliability issues, restrict the applicability of CIM-based NN. To address this issue and towards a low-cost NN hardware realization, in this thesis, we: a) thoroughly investigate the impact of RRAM faults on the inference accuracy of RRAM-based BNNs, and b) propose three complementary fault-tolerance techniques to mitigate the impact of RRAM faults on the BNN's accuracy. These techniques are namely: a) a fault-tolerant activation function, b) a redundancy and weight range adjustment scheme and c) a retraining technique. Evaluation results compiled on the MNIST, Fashion-MNIST, and CIFAR-10 datasets demonstrate that the proposed techniques can improve the inference accuracy in the presence of RRAM faults by up to 20%, 40%, and 80%, respectively. Moreover, comparisons with certain related state-of-the-art fault-tolerance frameworks indicate that the proposed techniques yield competitive results.

Recently, it has become popular to use Convolutional Neural Networks (CNNs) in embedded and portable devices. The popularity is based on their high accuracy rate in the field of Computer Vision (CV). However, CNNs are computationally intensive due to the convolutional layer, which accounts for over 90% of the operations. To overcome this problem, many researchers have exerted efforts to develop parallel and customised accelerators. Methods utilised in the accelerators range from bit optimisation to using fixed-point arithmetic, and to reducing the size of the network. Some researchers have also explored alternative computing paradigms such as Stochastic Computing (SC). The great advantage of SC is its ability to perform complex arithmetic with simple hardware. However, a major problem of SC is the trade-off between latency and accuracy. Thus, there have been several attempts to mitigate this factor, ranging from improving the generation of stochastic numbers to parallel bitstreams, to early terminations. This thesis proposes StoHej, a new SC multiplier design that combines stochastic bitstreams and complementary events. The multiplier has two input types, the first is the neural network feature value and the second is the weight value. The weight value determines how many iterations the computation requires. A complement event is utilised if the weight value is greater or equal to $0.5$ since the complement of the event yields a smaller number. Thus, the worst-case latency has been reduced from O(N) to O(N/2). The proposed multiplier was compared with a Conventional Stochastic Computer (CSC) multiplier and the BISC-MVM multiplier, which is the state-of-the-art for SC multipliers that uses an early termination mechanism. All multipliers were first tested in a software simulation in a general context. Accuracy and latency were measured in a software simulation. The results from these simulations showed a 3.2x speedup for the proposed design compared to BISC-MVM, with no increase in computational errors. Then, StoHej and BISC-MVM were tested in a CNN inference application with the MNIST dataset. The multipliers were used in a Multiply-Accumulate (MAC) array that was implemented on an FPGA. The results from the experiment show that StoHej had a 1.7x speedup and no loss in accuracy compared to BISC-MVM. StoHej's energy consumption was reduced by 40% when compared to BISC-MVM. The Area-Delay Product (ADP) of StoHej was 30% smaller than BISC-MVM. StoHej's Area-Delay-Energy Product is 2.3x smaller than the BISC-MVM multiplier.

The ρ-VEX is a processor designed at the Computer Engineering lab at TU Delft to be reconfigurable at runtime, resulting in a processor that can combine or separate instruction lanes according to the program requirements. The current cache for the ρ-VEX processor is direct mapped and always identical to the instruction group configuration. This is limited and not flexible, and a more flexible cache that can be reconfigured at runtime is desirable. This thesis introduces a more flexible cache, which is achieved by replacing the replacement policy with a more flexible variant, as well as adding an extra cache tree. The addition of the second cache tree allows for a more flexible cache size assignment, as either cache blocks of the small or the larger cache tree can be assigned to a specific instruction group. The assignments of the cache blocks can be reconfigured during runtime. The replacement policy is replaced by round robin and (pseudo) LRU, giving the required flexibility, as well as decreasing cache misses, which results in better overall performance for the $ρ$-VEX. Round Robin reduces the runtime when the application heavily uses the caches by 11.7%, but increases the runtime when the application has a low cache utilization. LRU always reduces the application runtime, and reduces the run times of cache heavy applications by about 13%.

Conventional Von Neumann machines inherently separate the processing units from the memory units. This architecture thus requires that data is transferred from the memory units to the processing units for performing computation, and results that should be stored are required to be transferred back to the memory units. Fast technological advances for processing speed have led to processors out-growing the speed at which data can be retrieved from the memory, meaning the bandwidth between the memory and the processor starts to bottleneck the system. This phenomenon is known as the Von Neumann bottleneck. Modern computer architectures utilize for example hierarchical memory architectures and pre-fetching schemes to alleviate the Von Neumann bottleneck. However, these methods do not succeed in fully removing the bottleneck. Furthermore, the energy required to retrieve data from the memory is several orders of magnitude higher than the energy required for a single operation within the processor. There is a clear need for a new computing paradigm to further progress modern computer architectures.

This thesis aims to progress work on a novel in-memory computation architecture by contributing towards the instruction set definition and hardware implementation of the architecture. Simulation results and a proof-of-concept hardware implementation have been used to investigate the power consumption, energy consumption and latency of the designed digital circuitry. These characteristics are found to not impose any road-blocks towards progressing the architecture to new levels in future works. This thesis is part of the overarching MNEMOSENE project of which, among many others, the Delft University of Technology is a parter.

An increase in the performance of mobile devices has started a revolution in deploying artificial intelligence (AI) algorithms on mobile and embedded systems. In addition, fueled by the need for privacy-aware insights into data, we see a strong push towards federated machine learning, where data is stored locally and not shared with a central server. By allowing data to stay on client devices and do training locally, we work towards a more privacy-friendly future. Furthermore, utilizing federated machine learning enables machine learning in data-constrained environments where bandwidth is not sufficient to upload the entire dataset. In this thesis, we look at the recent trend into less complex machine learning models. These models optimize resource usage while reducing accuracy loss. We investigate how these simpler models hold up within a federated setting. We also look into the developments of AI frameworks and their capabilities for mobile platforms. Based on these findings, we propose that model-hyper-parameter optimization is possible to maximize accuracy for smaller networks during federated learning. We show that it is possible to reduce the accuracy loss from 15% to only 0.04%. We then demonstrate what a mobile implementation looks like and the performance we see from an iPhone X. We show that an iPhone implementation takes less than 2x the amount of a regular laptop implementation. Finally, we demonstrate that we can reduce the model-size by up to 7x using modern weight quantization methods.

Hardware implementations of encryption schemes are unprotected against side-channel analysis techniques. Physical realizations of secure algorithms leak side-channel information through power, noise, time, sound and electromagnetic radiation. Data-dependent correlations with this leakage are exploited to obtain secret information. Power analysis techniques are powerful, undetectable and non-intrusive attacks that allow an adversary to extracts the secret key of the encryption scheme. These techniques rely on analyzing the power consumed by these physical realizations using leakage models and statistical techniques.

Implementing a countermeasure against power analysis attacks require a thorough understanding of the attack, encryption algorithm and it's implementation on hardware and software. Conventional countermeasures for AES against power analysis techniques minimize the side-channel information by implementing masking and hiding strategies at different abstraction levels. This thesis investigates a new class of countermeasures known as "breaking" through the implementation of the Substitution Box transformation using a neural network (S-Net). The inherent properties associated with the neural network architecture is expected to remove the correlation between the power consumed and the secret key used for encryption by breaking the linear power characteristics assumed by the leakage model.

The proposed approach was implemented in software and an attack framework is used to run side-channel attacks and quantify information leakage. The effectiveness of the implemented countermeasure is measured by checking and quantifying it's security against Differential and Correlation Power Analysis, Template and Deep Learning based techniques. The results indicate that the implementation is secure against these attacks.

As the digitisation of the world progresses at an accelerating pace, an overwhelming quantity of data from a variety of sources, of different types, organised in a multitude of forms or not at all, are subjected into diverse analytic processes for specific kinds of value to be extracted out of them. The aggregation of these analytic processes along with the software and hardware infrastructure implementing and facilitating them, comprise the field of big data analytics, which has distinct characteristics from normal data analytics. The systems executing the analysis, were found to exhibit performance weaknesses, significant front-end-bounding Level 1 Data cache miss rates specifically, for certain queries including, but not limited to, Natural Language Processing analytics. Based on this observation, investigations on whether, for data using the Apache Arrow format, its metadata could be used by certain prefetching techniques to improve cache behaviour and on the profile of the datasets and workloads which could profit from them, were conducted. Architectural simulations of the execution of various microbenchmarks in an In-Order and an Out-Of-Order core were performed utilising different popular prefetchers and comparing the produced statistics with those of a perfect prefetcher. During this process, the performance of systems featuring the tested prefetchers was found to lag behind this of the perfect prefetcher system by a considerable margin for workloads featuring indirect indexing access patterns for datatypes of variable width. As a result, those patterns, which are readily available in the access mechanism of Apache Arrow, were identified as possible candidates for acceleration by more sophisticated prefetching techniques. The first step in the investigation of such techniques was the introduction of a software prefetching scheme. This scheme, which is using prefetching and execution bursts, was embedded in a synthetic benchmark, specifically designed for the investigation of the effect the computation intensity of an algorithm has on the successful prefetching of indirect indexing access patterns. Its performance approached closely the performance produced by ideal prefetching for all the computation intensities except for the very low ones, with its resilience to possible variance in memory congestion being questionable though. As hardware prefetching is more adaptable to runtime parameters like memory congestion, subsequently such a module was designed, with information about the memory locations and hierarchy of the Apache Arrow columns’ buffers communicated to it by the software. Using this information, the prefetcher is able to distinguish between index and value accesses and prefetch the regular, iterative ones successfully. The hardware technique was able to almost match the performance of the ideal prefetcher for medium and high computation intensities and approach it, to the extent the bandwidth constraints allow, for the rest. In terms of speed-up, the maximum attained of the hardware prefetcher over the top performing reference prefetchers was almost 7x and 4x for In-Order and Out-Of-Order execution respectively with the software prefetcher performing marginally worse in both cases. Those speed-ups were achieved for those algorithm’s computation intensities which resulted in execution neither constrained by memory system’s bandwidth limitations, nor by in-core computation resources’ limitations.

Processor architecture is continuously evolving. As the trend predicted by Moore's law is nearing its end, the focus of designing processors has shifted from high-frequency single-core systems to the medium frequency multicore system to a relatively lower frequency many-cores system, in the hope of extracting more performance while keeping power consumption in check. To satisfy a spectrum of applications, modern processors employ central processing units (CPUs) for serving a wide variety of general-purpose applications, while general purpose - graphics processor units (GP-GPUs) are used for highly parallel applications. This thesis provides an alternative, called dynamic platform, by switching between a sequential processor for serving sequential applications and parallel processor for serving parallel applications on a Zynq FPGA (Field Programmable Gate Array). The first part of this thesis analyses and designs the model with suitable simulations to know the trade-offs. From the model, it is clear that towards the extreme ends of the application spectrum where either high level of parallelism exist or high level of sequential operations exist, GPU and CPU respectively outperform the dynamic platform. However, there exists a region suitable for the dynamic platform where the applications are neither too parallel nor highly sequential. To implement the model on FPGAs, suitable open-source softcores are researched and selected. ρ-VEX dual-core and Microblaze softcores are implemented for catering to sequential applications, and ρ-VEX many-core softcore is implemented for serving parallel applications. These softcores are evaluated against three benchmarks-- Image processing (parallel), CRC (sequential) and Hash (sequential). Finally, the dynamic platform analysis is done, and the results prove that on average the performance on the dynamic platform is better than considering either the sequential (ρ-VEX dual-core) or parallel (ρ-VEX manycore) platform alone. The speedup of the dynamic platform ranges from 1.45 to 2.9 (average: 1.61) with respect to sequential platform and from 1.02 to 1.60 (average: 1.44) with respect to parallel platform. In the current state of FPGA technology, the dynamic platform does not perform better than CPU and GPU on average for the considered benchmarks. The result is a fully functional open-source dynamic platform, which can switch between two (or three) architectures at run-time, depending on the application characteristic (sequential or parallel).

At the core of state of the art microelectronic industry's drive for better technology, lies the continuing advancement in the development of Integrated Circuits using highly complex lithography machines, known as lithosteppers, which embed complex mechanical sub-systems performing intricate motions.
These systems are controlled by means of custom real-time computing platforms containing off-the-shelf and specialized hardware components, and are optimized to keep pace with the continuing growing trend in performance requirements.
At the ASML Twinscan lithostepper's heart resides the Control Architecture Reference Model (CARM) motion control platform which manages, among others, the wafer-stage, a multiple degree of freedom module, able to position a 15 kg heavy wafer-table with nanometer accuracy at extremely high acceleration and velocity.
As the industry requirements for feature-size, overlay accuracy, and throughput keep increasing, the ASML lithosteppers, and the CARM platform in particular, should anticipate these demands by making early changes and upgrades with respect to computational performance and accuracy.
Given that the current lithostepper configurations are not capable of sustaining the anticipated updates, which requires the increase of the control loop execution frequency from 20kHz to 40kHz, an early evaluation of potential CARM High Performance Process Controller (HPPC) successors has been performed. This indicated that the NXP-Freescale T4240 processor can potentially fulfill the expected requirements, however, the evaluation lacks accuracy as it was performed on a benchmark code not reflecting the actual CARM workload. To circumvent this problem, in this thesis, we introduce a more accurate evaluation methodology, which relies on the actual motion control application running on the HPPC and is able to capture aspects as scheduling, parallelism, and processor resource usage.
To this end we develop a set of custom performance benchmarks able to emulate the CARM environment and evaluate the Freescale T4240 processor in this new context. Our results indicate that the T4240 is able to deliver enough computation power to fulfill the control loop execution frequency upscaling requirement from 20kHz to 40kHz.
Additionally, we demonstrate that due to its clustered hardware architecture one T4240 can sustain 20kHz loop execution frequency for the workload of three current HPPCs, which suggest that its utilization in current lithosteppers can be beneficial.

Image processing is found in many fields and in many domains. Advances in
digital image capturing technology allows for faster video rates, of higher quality, than has been seen before and that trend continues. With greater resolution and increased data flow there is also a need for faster and better hardware for image processing. As the trend introduced in Moore's law is slowing down, and possibly reaching saturation in the coming years, there is an ongoing search for new and different solutions in processor architecture. The trend went from single core to multi core and many core and now we are looking into other designs like memory streaming architectures and runtime reconfigurable computers. This thesis designs, implements and evaluates a programming interface for a dynamically-reconfigurable memory-streaming platform for image processing with a focus on programmability, power consumption, reconfigurability and performance. An application programming interface (API) is created to aid with new code development for the platform. The API is a library of functions that are run on an ARM processor and are used to setup, and communicate with, a stream of ρ-VEX soft processors running on a field programmable gate array (FPGA). In this research we look at other state-of-the-art solutions, for comparison and inspiration, that focus on programmability, reconfiguration and performance. The platform is reconfigurable at runtime and experiments show that it takes under 200 ms to completely reconfigure the fabric and initialize a new configuration of ρ-VEX processors. The platform is tested on a Zynq-7000 chip from Xilinx. Comparison is made between streaming architecture and a many core setup using the same amount of ρ-VEX soft processors. The results show a speedup of factor of 2 by using a single processing stream of seven cores compared with seven cores individually running the same algorithm. The result is a working fully-programmable and open-source streaming platform for the image processing domain.

Cardiovascular diseases are the leading cause of death in the devel- oped world. Preventing these deaths, require long term monitoring and manual inspection of ECG signals, which is a very time consum- ing process. Consequently, a wearable system that can automatically categorize beats is essential.
Neuromorphic machines have been introduced relatively recently in the science community. The aim of these machines is to emulate the brain. Their low power design makes them an optimal choice for a low power wearable ECG classifier.
As features are crucial in any machine learning system, this thesis aims at proposing an energy efficient feature extraction algorithm for ECG arrhythmia classification using neuromorphic machines. The feature extraction algorithm proposed in this thesis consists of the merger of a low power feature detection and a feature selection algorithm. Also, different network configurations have been investigated to achieve classification using an LSM architecture. The resulting system can accurately cluster seven beat types, has an overall classification rate of 95.5%, and consumes an estimate of 803.62 nW.