Carbon dioxide (CO₂) detection is vital in various fields, such as environmental monitoring, healthcare, and industry. Metal oxides are the sensing material because of their high sensitivity and stability. However, they have limitations in detecting CO₂ as CO₂ is a chemically stable gas, which can be mitigated by post-treatment such as annealing or doping noble metals. Spark ablation, a versatile technique for synthesizing nanoparticles with controlled size and composition, was utilized in this study to produce SnO₂ nanoparticles, which were subsequently integrated into a specifically designed interdigitated electrode (IDE) structure for CO₂ sensing. The IDE configuration featured a fixed finger width of 5 μm, with the gap width ranging from 2 to 15 μm, and devices were fabricated with SnO₂ sensing areas of 1×1 cm and 1×4 cm. Noble metals such as Ag and Ru were decorated on the SnO₂ layer to enhance the catalytic activity and promote the CO₂ adsorption reaction. Surface densities of Ag and Ru under various printing conditions were analyzed using spark ablation. Based on these results, decorated SnO₂ layers were fabricated with surface coverages of 19% Ag and 12% Ru, respectively. Annealing was performed later at 450°C and 600°C, and XRD results revealed that the grain size of SnO₂ increased from 7 nm at 450°C to 12 nm at 600°C. Gas tests conducted in an N₂ atmosphere demonstrated CO₂ detection at 200°C, with a higher response observed for samples with Ru nanoparticle decoration, approximately twice that of the undecorated sample. However, no recovery was observed. Overall, samples annealed at 450°C exhibited higher responses compared to the ones annealed at 600°C. In an N₂/O₂ atmosphere, the sensor exhibited almost no response to CO₂. Further investigation revealed a response to O₂, suggesting that the low operating temperature may hinder the reaction between CO₂ and adsorbed oxygen species, failing CO₂ sensing. An anomalous p-conductive behaviour was also observed in response to O₂. Experimental results showed no correlation between device area, gap width, and sensing performance.

Deposited dielectrics with low loss at millimeter-submillimeter (mm-submm) wavelengths are beneficial for the development of superconducting integrated circuits (ICs) for astronomy, such as filter banks, on-chip Fourier-transform spectrometers, and kinetic inductance parametric amplifiers. Although it is possible to fabricate microstrip lines using crystalline Si extracted from a silicon-on-insulator wafer by a flip-bonding process, deposited dielectrics al- low for simpler and more flexible chip designs and fabrication routes. In the ∼10–100 THz frequency range, dielectric losses are typically dominated by infrared absorption due to vibrational modes, whereas in the microwave fre- quency band (∼1–10 GHz) and at sub-Kelvin temperatures the dielectric loss is typically dominated by absorption due to two-level systems (TLSs). How- ever, the origin of the mm-submm (∼0.1–1 THz) loss in deposited dielectrics was unknown. In this dissertation we show that the mm-submm loss in de- posited dielectrics can be explained by the absorption tail of vibrational modes which are located above 10 THz. Furthermore, we found that hydrogenated amorphous silicon carbide (a-SiC:H) has a very low mm-submm loss tangent of 1.3×10−4 at 350 GHz, which makes it a promising low-loss deposited dielectric for mm-submm superconducting integrated circuits.

Based on a literature study we identified a-SiC:H and hydrogenated amor- phous silicon (a-Si:H) as potentially promising low-loss dielectrics. In order to find the origin of the mm-submm loss, and to define which materials we investi- gated in this PhD project, we characterized the dielectrics’ material properties at room temperature prior to performing the cryogenic loss measurements. We deposited a-SiC:H at a substrate temperature Tsub of 400◦C using plasma- enhanced chemical vapor deposition (PECVD), and we deposited the a-Si:H films at Tsub of 100◦C, 250◦C, and 350◦C. We characterized the films’ material properties using Fourier-transform infrared spectroscopy (FTIR), Raman spec- troscopy and ellipsometry. For the a-Si:H we determined the hydrogen content and the microstructure parameter from the FTIR data, the bond-angle disorder from the Raman data, and the void volume fraction from the ellipsometry data. For both the a-Si:H and the a-SiC:H we determined the band gap and optical refractive index from the ellipsometry data, and the infrared refractive index from the FTIR data. From the Raman spectra we observed that the a-SiC:H and the a-Si:H films were amorphous. Furthermore, we performed electron diffraction spectroscopy to determine the Si to C ratio of the a-SiC:H. For the a-Si:H we found that the all the material properties depend monotonically on Tsub. Additionally, we measured the cryogenic microwave loss of the a-Si:H films, but we found no correlation between the microwave loss and Tsub.

No cryogenic mm-submm and microwave loss data was available for a- SiC:H. We measured the low-power and cryogenic microwave loss of the a- SiC:H and found that the microwave loss tangent (tanδ ∼ 10−5) is compa- rable to the loss of a-Si:H. Furthermore, we measured the mm-submm loss in the range of 270–385 GHz using an on-chip Fabry-Pérot experiment. The observed mm-submm losss value of 1.2 × 10−4 at 350 GHz was significantly lower than what was reported for a-Si:H, which previously exhibited the low- est reported microwave and mm-subm wave loss values among the deposited dielectrics which are commonly used in superconducting ICs. Furthermore, we found that the mm-submm loss of the a-SiC:H increases monotonically with frequency. This was surprising in the framework of TLSs and led us to the hypothesis that another loss mechanism than TLSs might be dominant at mm- submm wavelengths. In addition to the low losses, the a-SiC:H was found to be beneficial thanks to its very low stress, lack of blisters, and the possibility to fabricate a membrane from the a-SiC:H on a c-Si wafer.

To study the origin of the frequency dependent mm-submm loss in the a- SiC:H, we extended the on-chip Fabry-Pérot experiment to the 270–600 GHz range by making use of a wideband leaky antenna. Additionally, we measured the complex dielectric constant of the a-SiC:H in the 3–100 THz range using Fourier-transform spectroscopy (FTS). We modeled the FTS data using the Maxwell-Helmholtz-Drude (MHD) dispersion model and obtained the complex dielectric constant in the 3-100 THz range. Finally, we modeled the combined on-chip loss data from the Fabry-Pérot experiments and the FTS data by fitting the MHD dispersion model in the frequency range of 0.27–100 THz. Our model demonstrates that the mm-submm loss in the a-SiC:H above 200 GHz can be explained by the absorption tail of vibrational modes which are located above 10 THz. These results pave the way for a thorough understanding of the mm-submm loss in deposited dielectrics.

The low losses of the a-SiC:H allow for integrated superconducting spec- trometers with a large frequency bandwidth and relatively high resolving pow- ers without sacrificing too much optical efficiency. This has led to the application of the a-SiC:H in the DESHIMA 2.0 filter bank, which has seen first light in 2023 at the ASTE telescope in the Atacama Desert.

Graphene, despite its exceptional electrical properties, is not suitable as a channel material in field-effect transistors due to its zero band gap. Engineered graphene structures, such as graphene nanoribbons, have been proposed to overcome this limitation. However, nanoribbons, while offering an opened band gap and favourable current on/off ratios, suffer from low individual driving currents. Graphene nanomesh provides a potential solution by maintaining the benefits of nanoribbons while offering higher driving currents due to its two-dimensional structure. However, fabricating graphene nanomesh remains challenging.
This study investigates the fabrication of graphene nanomesh using a transfer-free anodization method with nanoporous anodic alumina as a hard mask in a plasma etching process. Unlike previously published methods, which require the transfer of brittle alumina masks, this work develops a process where anodization is performed directly on aluminium deposited on top of graphene. A two-step anodization process was tested and optimized using aluminium on silicon samples, including the development of a partial stripping variation aimed at preserving pore ordering.
Initial tests on Al-on-Si samples demonstrated promising results, with plasma etching yielding uniform patterns when using the partial stripping technique. However, when applied to graphene samples, significant challenges were encountered. Poor adhesion between aluminium and graphene layers resulted in delamination and bubbling during anodization, disrupting the pore formation process and leading to defects. Efforts to improve adhesion through patterning of the substrate showed no substantial improvements. However, it was confirmed that the Mo and the graphene survived the anodization process.
Although plasma etching produced positive results in regions where delamination was minimized, etching on graphene samples remained inconsistent. Despite these challenges, the study provides valuable insights into the fabrication process, particularly regarding mask stability and adhesion issues.

In the semiconductor industry, the ongoing demand for the miniaturization of electronic devices has significantly increased the number of components integrated into a single wafer. Consequently, the dimensions of interconnects in integrated circuits (ICs) must be minimized to connect more transistors. This trend inevitably leads to a substantial rise in current density within the interconnects, posing a major reliability challenge known as electromigration (EM). EM can result in further reliability issues, ultimately causing device failure. Extensive research has been conducted over the past decades to mitigate the impact of EM.
This study focuses on copper (Cu) interconnects, investigating the effect of annealing on their microstructure and the resulting impact on resistivity, with particular emphasis on how the microstructure influences EM. Additionally, the progress of attempting to forming Cu nanotwins via electroplating to resist EM is briefly investigated. Sputtered Cu was annealed at temperatures of 300℃, 400℃, 500℃, and 700℃, and the resulting microstructural variations were characterized by using EBSD. The findings reveal a progressive strengthening of the (111) texture in Cu film and an increase in grain size with higher annealing temperatures. Additionally, a notable decrease in grain boundary length was observed as the annealing temperature increased, correlating with reduced resistivity across the annealed samples. Moreover, the study highlights a elimination of defects and strain within the Cu films with increasing annealing temperatures.
Furthermore, EM measurements were conducted using accelerated tests under conditions of high current stress and high temperature. The variations in the microstructure of Cu films were described, and the correlation between EM mechanisms and microstructural parameters was discussed. To quantify the progress of EM, the drift velocity for each sample was calculated, revealing a trend of slower drift velocities with increasing annealing temperatures. This work provides a unique opportunity to investigate the impact of annealing on the microstructure of Cu interconnects and to study how these changes influence EM performance. The findings contribute to a deeper understanding of EM and enhanced reliability prediction in electronic devices.

Keywords: electromigration, copper interconnects, microstructure, annealing.

Chip forensics has become an important aspect of law enforcement for retrieving data from data carriers. Improving data encryption techniques, smaller technology nodes and increasing chip design complexity instigate the constant need for new software and hardware hacking methods. The work presented in this thesis investigates the potential of a new hardware hacking method named backside contacting. This method aims to connect a probe to one of the bottom interconnects through the backside to listen to the signals sent over that interconnect.
For this purpose, a recipe has been developed. This recipe is a workflow of numerous processes and steps. Several methods like delayering, cross-sectioning and infra-red (IR) imaging were developed to obtain information about the layout and technology of the chip. Atomic layer deposition (ALD), induction coupled plasma enhanced chemical vapour deposition (ICPECVD) and a focussed ion beam (FIB) were used to create structures on the die, in order to realize a backside interconnect. Finally, various setups were built to test the chip throughout the recipe.
The study shows that each step is possible without losing the data on the chip. The yield of surviving chips after each step, however, should be increased to establish a full backside contact while keeping the chip alive. The study also indicates that there remains considerable potential for improvement within each step. The results are promising and justify further research into the method of backside contacting.

This Bachelor of Science thesis presents the development of a portable readout system for a graphenebased gas sensor array, aiming to bring advanced gas sensing technology from a controlled laboratory environment to practical field applications, such as greenhouses and vineyards. The project focuses on integrating various hardware components into a single printed circuit board (PCB) equipped with a microcontroller, ensuring accurate resistance measurement of graphene strips, generating programmable waveforms for micro hotplate control, and facilitating data communication via USB and Modbus interfaces. The design includes high-resolution analog-to-digital converters (ADCs) for precise current and voltage measurements, a digital-to-analog converter (DAC) for waveform generation, and a robust power management system supporting multiple power inputs. The system supports dual operation modes: interfacing with a desktop for laboratory use and functioning autonomously as an integrated sensor unit. Key challenges addressed include ensuring measurement accuracy, reliable sensor array connectivity, and user-friendly interfacing for both lab and field scenarios. Comprehensive test plans are outlined to verify the system’s performance, focusing on critical requirements such as resistance measurement accuracy, waveform generation, and communication interfaces. The successful implementation of a large part of this readout system demonstrates its potential for enhancing gas detection and monitoring in agricultural applications, providing a scalable solution for future deployment and development.

As advances in silicone CMOS technology steadily plateau, new avenues of electronics design must be explored. Graphene Nanoribbons (GNRs) are a potential solution. Current GNR designs require wasteful exhaustive searches for the required device topologies, limiting the size of the solution space that can be searched. This is fine for simple circuits, but more complex functionality requires a different approach. This work presents a new way of identifying suitable GNR device topologies for any functionality. It also presents an example of this, demonstrating how a circuit using the resultant GNR devices can outperform conventional, more complex circuits.

The proposed methodology uses an evolutionary algorithm to efficiently search a large solution space of possible GNR device topologies. This is done while only having to simulate the behavior of a minuscule fraction of the device topologies in this solution space. The GNR devices found by this evolutionary algorithm are used to implement a 4-bit Analog-to-Digital Converter (ADC), where each bit of the circuit consists of only a couple of GNR devices, in contrast to the many more transistors required for conventional designs.

The resulting ADC circuit performs better than conventional ADC designs in terms of energy cost, conversion delay, and required circuit area by several orders of magnitude.

Electronic interfaces, particularly microelectrode arrays (MEAs), are crucial for studying electrophysiological processes in the body, with applications ranging from implants to deep brain simulators. In neuroscience, they play a vital role in exploring neuronal cell distribution and behaviour, as well as disorders like epilepsy and Alzheimer’s disease. However, electrophysiological recordings have limitations, that have led to the exploration of optical approaches like calcium imaging. To address the shortcomings, a promising strategy involves integrating electrophysiology and optical methods for simultaneous cellular activity measurement, capitalising on their combined temporal and spatial resolution. The challenge lies in developing fully transparent MEAs to overcome the limitations of traditional opaque electrodes.
Graphene’s versatile properties, spanning from electrical conductivity to mechanical flexibility, position it as an ideal material for transparent and flexible electronics, particularly in neural recording and stimulation. Due to these properties, graphene MEAs (gMEAs) allow integration with various optical techniques, overcoming limitations associated with traditional opaque MEAs.
In this project, we designed and fabricated a transparent gMEA, intended to perform electrical signal recordings and optical voltage mappings simultaneously from photostimulated optogenetic cell lines. The design allows for photostimulation from a source beneath the gMEA, while enabling unobstructed optical measurements from above. The electrodes were crafted from multilayer chemical vapour deposition (CVD) graphene, chosen for its transparency and favourable electrical properties. Quartz and sapphire were evaluated as potential substrates for the device. After demonstrating the synthesis of multilayer graphene was possible on both substrates, quartz was selected as the preferred material due to its resistance to graphene delamination.
Characterisation of the gMEAs was done using various techniques, including optical transmittance (OT), electrochemical impedance spectroscopy (EIS), and measurements of the signal-to-noise ratio (SNR). The stability of the gMEAs was also assessed by immersing the devices in cell culture medium and with ageing tests performed in PBS. Initial electrochemical characterisation of the gMEAs exhibited promising signal detection despite a relatively high baseline noise of ∼ 23 μV . In comparison, commercially available MultiChannel Systems MEA (60MEA200/30iR-Ti), showed a lower baseline noise (∼ 4 μV ), but gMEAs achieved comparable signal sensitivity. EIS of gMEAs revealed an impedance at 1 kHz ranging from 3.2 to 9.89 MΩ, largely surpassing values in other studies. However, when area normalised, the impedance remained comparable to reported values. Stability tests identified issues related to the permeability of the encapsulation layer and degradation of molybdenum structures, causing large variations in the SNR and EIS measurements after exposure to liquid media.

Resolving the underlying mechanisms of complex brain functions and associated disorders remains a major challenge in neuroscience, largely due to the difficulty in mapping large-scale neural network dynamics with high temporal and spatial resolution. Multimodal neural platforms that integrate optical and electrical modalities offer a promising solution, with microelectrode arrays (MEAs) being particularly effective for capturing electrophysiological activity across multiple neurons at the cellular level. Graphene has emerged as a highly attractive material for such neural interfaces due to its unique combination of biophysical, electrical, mechanical, biological, and optical properties. However, current graphene-based electrodes face challenges, including the need for transferring pre-grown graphene layers, which causes reliability issues.

In this work, microelectrode arrays based on transfer-free multilayer graphene and PEDOT:PSS are developed, and their feasibility for in vitro neural activity detection is evaluated through a brain slice culture. Firstly, the design and fabrication of graphene-based MEAs (grMEA) on transparent substrates is presented, establishing optimized microfabrication procedures for the integration of transfer-free multilayer graphene technology on in vitro MEAs. Several electrode diameters, ranging from 10 μm to 500 μm, are included to accommodate different experimental requirements and test the limits of the technology. Second, the combination of graphene and PEDOT:PSS conductive polymer is explored to overcome the fundamental limitations associated with graphene electrodes, such as high impedance at small electrode sizes, without compromising the optical transparency. A technique to integrate patterned PEDOT:PSS polymer coating on the electrodes to form graphene/PEDOT:PSS microelectrodes
(grppMEA) is developed.

The electrochemical performance, including charge storage capacity (CSC) and impedance properties, of the grMEA and grppMEA devices are evaluated. Obtained results, comparable with state-of-the-art neural interfaces, show that the PEDOT:PSS coating increases CSC values more than the double and substantially reduces the impedance by 10-20 times (e.g., from 247 kΩ to 13 kΩ for 50 μm diameter electrodes). This demonstrates the potential of the devices for efficient electrical coupling with neural tissue. Additionally, the volumetric capacitance of grppMEA electrodes was found to be 55.7 F/cm3, highlighting the volumetric ionic-electronic interaction coming from the PEDOT:PSS film, a feature absent in metal electrodes.

A custom-made interface that effectively connects the MEA devices to specific recording systems is developed to enable the acquisition of neural signals. The electrophysiological recording capabilities of the grMEA and grppMEA devices were subsequently evaluated through in vitro cerebellar brain slice cultures. Acute recordings of spontaneous activity and spike pattern characteristics of Purkinje cells and other neurons have been successfully obtained. The obtained signal-to-noise ratio values, ∼ 30 dB, demonstrate the great recording potential of the proposed MEAs. Overall, the results presented in this work demonstrate that transfer-free multilayer graphene MEA technology, especially when combined with PEDOT:PSS, overcomes the current limitations and offers the possibility for high-density recordings with single-cell resolution.

Graphene-based neural interfaces offer an innovative solution to surpass the resolution limit of traditional neural recording, integrating neuroelectronics with optogenetics for combined electrophysiological and optical neural monitoring, among others. Three important factors in these interfaces are achieving a high signal-to-noise ratio (SNR), maintaining effective stimulation properties, and ensuring strong cell adhesion to neural tissue, which can be enhanced through surface topography modifications. This work explores two main approaches to enhance graphene-based neural interfaces: (1) exploring the creation of thin graphene films on molybdenum to integrate transistors and electrodes within a single fabrication process, which can potentially enhance the signal-to-noise ratio (SNR) while maintaining stimulation efficacy; and (2) creating corrugated graphene structures that increase surface area and improve cell adhesion. A major challenge in this work is establishing a transfer-free chemical vapor deposition (CVD) process on molybdenum for both approaches. While this method offers significant benefits, such as reducing defects and contamination, the challenge lies in the limited understanding of the mechanisms behind graphene growth on this catalyst. Exploring new molybdenum configurations to provide a better understanding of the graphene growth mechanism on this catalyst is also a relevant part of this work.
Experiments revealed that graphene grown on thick, unpatterned molybdenum produced high quality few layer graphene (FLG), while patterned thick molybdenum produced multilayer structures with high defect density. Based on the results obtained, a mechanism for graphene growth on thick molybdenum catalysts is proposed. However, the decision was made to proceed with the second research approach due to time limitations. Considering corrugated graphene structures, Raman analysis showed higher-quality graphene layers within the valleys, fact that supports the proposed growth model. sheet resistance values ranged from 60 Ω/sq – 180 Ω/sq, being these values among the lowest reported in the literature for undoped graphene. These low values are attributed to the combination of an FLG graphene with good interlayer electronic coupling, which is possible because of the low number of defects in the material. Results are promising for enabling high-density optically transparent neural interfaces with graphene tracks. Additionally, small and denser corrugations enhanced the electrode surface area, showing reduced impedance at 1 kHz compared to flat electrodes. Electrodes with 1 μm, 5 μm, and 20 μm corrugations shown impedance reductions in comparison to flat electrodes, demonstrating an increased surface area. The area normalized impedance decreased from 35.5 kΩ ± 0.7 kΩ for flat electrodes to a minimum of 26.2 kΩ ± 1.1 kΩ. The electrodes achieved a maximum charge storage capacity (CSC) of 80.6 μC/cm2 and a maximum charge injection capacity (CIC) of 7.71 μC/cm2, which are lower than the threshold for stimulation applications. However, these values could be potentially optimized through fabrication refinement. Furthermore, the biocompatibility tests indicated that corrugated graphene patterns are biocompatible have the potential to actively influence stem cell cytoskeleton dynamics, highlighting their promise as a safe and novel inclusion in interfaces for next- generation neural applications.

IN advancing the ’More thanMoore’ paradigm, heterogeneous integration has emerged to facilitate the creation of highly efficient, compact, and multi-functional semiconductor systems. Addressing the challenges related to power efficiency, superior performance, and integration density, low-temperature nanoparticle sintering technology has become pivotal for integrating diverse materials and components in advanced semiconductor packaging. Traditional electronic packaging materials face limitations and process complexity, making low-temperature nanoparticle sintering an attractive option. With its benefits of low processing temperatures (< 0.4 Tm), exceptional electro-thermomechanical performance, and high process flexibility, this technology is gaining increasing attention, particularly in high-power electronics packaging applications. Over the past decade, silver (Ag) sintering technology has shown promise in the power electronics industry, serving as an effective solution for high-power die-attach. However, due to the high cost of materials, efforts have been directed towards pressure reduction and exploring alternative sinter materials to reduce overall process costs. In recent years, the concept of ’all copper (Cu) interconnect’ has transcended fromlow-power to high-power applications, with low-temperature Cu nanoparticle sintering showing substantial potential as a replacement for Ag in pressure-assisted sintering. Despite this promising avenue, the understanding of sintered Cu materials remains limited, primarily due to susceptibility to oxidation issues. Comprehensive studies comparing both sinter materials, extending beyond mere shear tests, are insufficient, leaving a significant gap in our understanding. Furthermore, methodologies for characterizing the sintered structure and providing detailed insights into its thermo-mechanical behavior are notably absent. In this dissertation, molecular dynamics (MD) simulation was employed at first to study the nanoparticles’ coalescence kinetics and mechanical and chemical performance of coalesced nanoparticles. A two-hemispherical nanoparticle model was built to simulate the impact of sintering temperature and pressure on low-temperature pressureassisted coalescence. The sintering dynamics and microstructure evolution were analyzed, including neck growth, shrinkage variation, grain boundary development, and dislocation activities. Furthermore, on the basics of pressure-assisted sintered nanoparticles, uniaxial tensile tests with a constant strain rate were employed to investigate its tensile performance. Subsequently, another mechanical nanoindentation simulation was implemented in a multi-nanoparticle sintered structure. The impact of indentation position and indenter size on the nanoindentation response was investigated. At the end of the first chapter, the chemical corrosion of sulphidation on multi-Ag nanoparticles’ sintered structure was simulated by the reactive-force-field (ReaxFF) MD method. The sulphidation on the dense Ag and porous sintered structures was compared and analyzed. Moreover, the sulphidation mechanism was revealed at an atomic level...

As silicon carbide(SiC) gets more and more attention from the semiconductor industry due to its robust mechanical and chemical properties, reliable and standardized processing technologies such as reactive ion etching(RIE) for SiC are in great demand. This is because of the difficulty and challenge of fabricating micro devices on the SiC substrate. Although the high hardness and chemical inertness make SiC a good candidate for applications such as sensors in harsh environments, they also impede the development of SiC-based devices when considering processing. This thesis aims to develop a standardized inductively coupled plasma(ICP) reactive ion etching(RIE) process for 4H-SiC substrate etching. The developed process is expected to be applied in the fabrication of micro-electro-mechanical systems(MEMS). The specifications are a high etch rate, micro-masking-free surface, and high selectivity. First, a literature review was conducted to comprehensively study the characteristics of the SiC material and the mechanisms of the ICP RIE process. Second, a baseline recipe was developed guided by the theory studied in the literature works. Third, initial tests were conducted, and the preliminary optimizations with a focus on etch rate and micro masking suppression were performed. Fourth, the design of experiments(DOE) based on the preliminarily optimized recipe was conducted to study the effect of process parameters on etch rate, etch profile, and selectivity. Last, the optimized recipes with a focus on etch rate, etch profile, and selectivity were summed and listed. The achieved maximum etch rate was 1.26 µm/min. The maximum selectivity of the hard mask material to SiC was 153 when the nickel hard mask was used. Amicro-masking-free surface of SiC was achieved.

Numerous advancements have been made in transparent electrode technologies that can complement optogenetics and imaging modalities. However, several obstacles restrict the design and material of electrode devices, including the required flexibility, transparency, low impedance, high charge storage
capacity (CSC), and high charge injection capacity (CIC), among others. The impedance of transparent graphene arrays is higher, and its CIC is significantly lower than platinum, a metal typically employed for electrophysiological recording and stimulation. It is possible to enhance the electrochemical properties
of planar, transparent graphene electrodes by functionalizing their surfaces with platinum nanoparticles (Pt NPs), effectively increasing the electrode surface area. Existing research on platinum nanoparticles on transparent graphene electrodes has solely focused on simultaneous electrical recording and optical imaging of neuronal activity. There is currently no quantitative evidence of the extent to which platinum nanoparticles can impact the stimulating properties of transparent graphene electrodes and any indication of the stability of the coating. Therefore, material and electrochemical device characterizations were conducted to compare the recording and stimulating properties of graphene versus graphene with Pt NPs of varying surface densities.

Graphene as an allotrope of carbon is promising for the detection of gaseous molecules due to its extremely high surface-to-volume ratio. However, its low selectivity poses a major problem for practical applications. The work presented in this thesis addresses the selectivity problem by depositing metal/metal oxide nanoparticles (NPs) on the surface of graphene. For this purpose, gas sensors with multiple multi-layer graphene (MLG) strips were fabricated. Four types of metal/metal oxide nanoparticles were investigated: Gold (Au), Platinum (Pt), Copper (Cu), and Iron (Fe). Various techniques were developed to study the properties of graphene and NPs. In addition, an automatic measurement setup with multi-strips switching is developed for data acquisition. Finally, the sensors decorated with different metal types and coverages are investigated for their response to H2O and NO2. The study shows that both the pristine devices and the sensors decorated with NPs hardly response to water molecules, while the responses to NO2 are larger and vary depending on the NPs. The results are promising for the development of a gas sensor array based on this methodology with improved selectivity for gas detection.

The evolution of microphone technology can be linked to the growing multimedia and communication market. The first is linked to the music and audiovisual industry, while the latter is linked to smartphones, smart mobility, and home automation. In all of these audio applications, the common trend is toward downsizing and performance improvement.
State-of-the-art silicon and nickel suspended membranes generally require a large diameter (in the millimeter range) to ensure high sensitivity. To this end, new materials have been studied. The properties of these materials should allow for miniaturization without losing performance.
As a matter of fact, over the past decade, researchers have been studying how to implement graphene in sensing applications. The properties of graphene have enabled the realization of a number of devices capable of outperforming their silicon counterparts while decreasing the sizes of the sensors.
The properties of these new materials should allow for greater flexibility and a thinner membrane that will ensure a greater mechanical response. This will allow for the creation of a smaller membrane. On the other hand, suspended graphene-based as membranes of a capacitive microphone generally featured a low-yield process in which the graphene is transferred from the grown substrate to the target device using polymers. The low-yield is related to a not fully automated transfer method. These restrictions limit the mass production of these devices, making large-scale production difficult.
Therefore, a possible method to obtain a transfer-free, wafer-scale, high-yield process for the realization of a graphene-based capacitive microphone is presented. The use of graphene will allow for miniaturization and improved performance.
The presented work will be structured as follows:
Chapter 1 - Introduction: The rationale for the thesis is provided, underlying the advantages of using graphene in the applications of capacitive microphones. The physics and history of capacitive microphones will be explored. A method to improve the sensitivity while scaling the device will be investigated. The research questions that started this thesis work are listed.
Chapter 2 - Literature Review: A study on state-of-the-art capacitive microphones will be introduced, focusing on the transfer and transfer-free methods for the realization of graphene-based capacitive microphones. The knowledge gained will provide an overview of the beneficial properties of graphene in condenser microphone devices.
Chapter 3 - Device Simulations & Concept Design: The device will be simulated with 2 different models. The used models will define the geometry of the final device. Subsequently, the design of the mask will be presented. An overview of the used materials and the reason behind their choice will be presented.
Chapter 4 - Fabrication Results: Some tests will be exposed and the process used for the realization of the final device will be presented, highlighting all the critical steps of the presented flowchart.
Chapter 5 - Measurement of the Processed Device: The results and the measured data will be discussed.
Chapter 6 - Final Conclusions & Future Perspective: The results of the presented work will be highlighted and suggestions for a future improvement of the device will be presented.

Metal oxide nanoparticle gas sensors showpromise due to their high sensitivity towards a wide range of gases, low costs, and low complexity. Particle sizes at nanometers offer a high surface-to-volume ratio which provides more areas on the surface where reactions can occur. This work presents the application of spark ablated nanoparticles on chemiresistors and chemFETs, and does a study on whether spark ablated nanoparticles are a viable alternative to nanoparticles generated using other methods. The focus in this thesis is on pure metal oxide nanoparticles without any addition of dopants or decorations. Devices are fabricated with different interdigitated electrode dimensions. The effect of electrode width and gap size on the gas response is studied by comparing the sensing performance of the devices. In this work, a very high sensitivity of 1300% is achieved towards 35% relative humidity using a 1x1 mm device with SnO2 nanoparticles. Towards 20 ppm of ethanol, sensitivities of 39% and 67% are achieved using 1x1 mm and 4x1 mm devices with SnO2 nanoparticles respectively, which implies that spark ablated nanoparticles could be a viable alternative to particles generated using other methods. The full recovery time after gas exposure seems to be very long and takes around an hour for some devices at 200 °C. Possible solutions for this are setting a higher temperature (not possible with the used setup), or reducing the particle size (∼20 nm in this study). The electrode finger widths and gap sizes are varied between 2-15 μm for each device. However, no correlation is found between electrode geometry and gas response within this range, suggesting that differences in gas response between devices likely stem from nanoparticle layer quality differences.

To extend Moore’s law, silicon carbide devices attend the researcher’s attention due to their irreplaceable advantages such as high critical breakdown electrical field, wide bandgap and excellent thermal conductivity without sacrificing too much charge carrier mobility. However, the defects on the SiC-oxide interface degrades the performance of the device and even get worse at high temperature, such as the threshold voltage shifting problems, limiting the design of the integrated circuits. The thesis models, characterise, analyses, measures and extracts the traps of SiC MOSCAP, to understand the trapped charge transportation and unreliability mechanism under high temperature.
Effectively using SiC materials necessitates the need to understand the physical properties itself. Due to the large bandgap, the inversion layer cannot be observable in low frequency C-V measurement. The electrical field, space charge region, surface potential and C-V curve in SiC devices all differ from Si devices. More importantly, the trapped charges fluctuate the surface potential of the SiC devices. To give insight into the mechanism governing the trapped charges, the mathematical solution of the trapped charges in the whole bandgap is solved.
To be specific, the trap behaviour at a single energy level is then followed. A nonzero transient current is generated due only to the capture and release of the trapped charges when the equilibrium condition is broken. The trapped charges with high energy are thermalized and an equivalent admittance is obtained which further be split into a capacitance and a conductance.
Rising temperature activates the dopant atoms that are not ionised, and the Fermi level shifts towards the midband. The variation of equivalent circuit components and physical parameters responds to the temperature. High temperature expands the SiC crystal and the trapped charges are easy to receive energy from phonons so that the interaction between traps and the conduction band is enhanced and more empty states are waiting for the recombination of the charge carriers.

Graphene is two-dimensional allotrope of carbon with a honeycomb-like lattice structure. It shows exceptional properties in electrical, optical, thermal, mechanical and chemical fields. And due to its excellent properties, it is being researched to be used in many applications such as, sensors, graphene transistors, opto-electronics, etc. To realize these applications in an industrial scale, reliable methods to grow and transfer graphene need to be developed. Methods such as chemical and mechanical exfoliation, chemical vapour deposition (CVD), etc. are a few methods which are used to synthesize graphene. And wet transfer, electrochemical delamination, etc, are a few methods to transfer graphene on to the required substrate. Graphene is sensitive to chemicals and processing steps, hence the properties/behaviour of graphene varies based on the fabrication and transfer technique used. Applied Nano-Layer(ANL) is a company based in Delft, that fabricates and transfers wafer-scale mono-layer graphene. Asmentioned before, the properties/behaviour of graphene changes based on the fabrication and transfer technique used. Therefore, in this thesis, the properties/behaviour of monolayer graphene provided by ANL, is analyzed. In this thesis, electrical properties like channel resistance, resistivity and mobility were analyzed. Also, the optical behaviour of graphene where pauli-blocking stops the absorption of light at dirac point, is analyzed. Few questions related to design of the process flow, working of the fabricated devices, propagation of light in the waveguides, modulation of light and effect of process flow on graphene, were answered to properly analyze the above stated properties/behaviour of graphene. First, a wafer-scale silicon waveguide was designed using COMSOL and BeamLab. The derived width of the waveguide was found to be for the values of 1 um to 4 um and the optimal cladding thickness was found to be 20 nm. Then, the designed waveguide structures were translated onto a mask that would be used in the fabrication of the electro-absorption modulators. Second, a cleanroom compatible process flow for the fabrication of Hall bars and electro-absorption optical modulators was designed and optimized. Several testing steps were performed to find the optimal parameters required in the process flow. Third, the hall bars and the optical modulators were fabricated in the clean room , Else-Kooi Lab(EKL), using the designed masks and process flows. The electrical properties were analyzed by extensively measuring the hall bars. As an example, the average channel resistance, dirac voltage, average resistivity and average mobility of a graphene hall bar with dimensions 2 um x 2 um was measured/calculated to be 6.74 k­, 75.9 V, 1.7 k­ and 1573.28 cm2/Vs respectively. Similarly, the values for 11 other dimensional devices were measured/calculated. The optical behaviour was analyzed by testing the electro-absorption optical modulator. A few waveguides were tested for propagation of light and a power of 0.8 uW wasmeasured for an input power of 0.6mW, which suggests that light successfully propagates though the waveguides. Graphene modulation was tested using back gate biasing and an average dirac voltage of 73.33 V was observed for 2 um x 2 um hall bar device on the optical modulator die. These two when done simultaneously theoretically should modulate light. Lastly, the impact of process flow on graphene/ graphene devices was checked. And a drastric fall to 30% working devices(for optical modulators) from 60% working devices (for hall bars) with increase in process flow steps concludes that the number of processing steps does affect the graphene/ graphene devices.