High conversion efficiencies and low production costs have placed Silicon heterojunction (SHJ) solar cells as one of the top contenders in the photovoltaic market right now. When combined with the interdigitated-back-contacted (IBC) architecture, SHJ-IBC cells set world record efficiencies for silicon cells: in 2024, the record stands at 27.3% efficiency. However, the IBC architecture introduces complex processing steps. The goal of this project is the simplification of processing steps of SHJ-IBC solar cells, obtained with the use of hard masks for the direct deposition of patterned layers.

The first part of the project is focused on the development of hard masks. First, silicon based hard masks have been fabricated using wet and dry etching methods. Their fabrication process has been optimized until high quality masks with low defect rates have been achieved. In addition to these masks, quartz mask samples provided by a third party have been tested. Deposition of 50 and 100nm of (n) nc-Si:H have been made with all masks to evaluate their potential based on their resolution, quality, reusability and price. While quartz masks have demonstrated to be very promising and industry orientated, the best trade-off of qualities in a research environment has been found in dry etched silicon masks.

In the core of the project, dry hard masks have been used to substitute two photolithography steps in the fabrication flowchart of IBC-SHJ solar cells in order to achieve a significant process simplification. The use of hard masks has brought relevant impacts to the SHJ-IBC cell fabrication, like the removal of wet etching steps that can potentially bring uncertainty to process flowchart and the reduction of the processing time to half of what it was before the use of hard masks. Regarding the depositions made through the hard masks, the challenges of obtaining a precise alignment and accurate feature sizes been assessed. The implication of those challenges in the performance of the solar cells has been then evaluated.

Lastly, the thesis introduces a simplified fabrication process of SHJ-IBC solar cells with the implementation of hard masks. With the new fabrication process, efficiencies of up to 5.47% have been demonstrated. Through the introduction of the SHJ-IBC flowchart based on hard mask patterning, the project contributes to the ongoing effort to bring SHJ-IBC cells closer to the industry.

Neuromorphic computing, a novel computing configuration inspired by the brain, aims to perform calculations based on physical neurons and synapses, attracting significant attention in recent years. Resistive random access memory (RRAM) shows great potential in this field, demonstrating high operation speed, nanoscale scalability, long retention time, non-volatile performance, and a simple structure.

Despite the promising performance of RRAM, a high forming voltage potentially hinders the widespread application of the device. This thesis aims to diminish and eliminate the forming voltage. To achieve this, different metals were inserted between the insulator layer and the bottom electrode of the RRAM, serving as an interface metal layer. The interface metal was expected to introduce oxygen vacancies to the insulator, thereby decreasing the forming voltage. Advanced nanofabrication processes were employed in the cleanroom, and a related recipe was developed. The influence of layer thickness and device area was also studied to gain a comprehensive understanding. Among all the samples, Ru-based devices were observed to be forming-free.

Data analysis methods were applied to model the data, with the random forest method found to be the most suitable, achieving an accuracy of 82.4%. The model was verified by measurements of 10 nm Ru-based devices. Feature importance was then calculated to interpret the model. The four most important features determining the forming voltage are the thickness, standard electrode potential, area, and work function of the interface metal. This work adopts a new approach to eliminating the forming voltage, not only providing a forming-free device but also offering a guideline for future research on forming voltage.

True Random Number Generators (TRNG) are fundamental cryptographic primitives. They are needed, for example, to generate cryptographic keys and numbers. Poor random number generation can lead to weaknesses in the cryptographic system. A good example can be found in the work of Heninger et al., who managed to retrieve large amounts of private RSA keys due to entropy problems in random number generators used for key generation.

Statistical test suites such as Dieharder and NIST SP 800-22 can be used to determine whether random number generators provide the required entropy. To improve such an evaluation, which is necessary for high-assurance applications, a stochastic model of the noise source must be developed as described, for example, in AIS 20/31.

The research presented in this thesis focuses on designing and validating a noise source based on counting ring oscillator periods. The work presents an analysis of this ring oscillator-based design, consisting of stochastic models, entropy evaluations, high-level and SPICE simulations, and hardware validation using the Intel Arria 10 FPGA platform.

Using the developed models, this work (i) quantifies the improvement in randomness due to sampling the noise source with a second ring oscillator, (ii) establishes a lower bound for the min-entropy of the noise source, and (iii) shows that the design benefits from using ring oscillators with shorter periods and, thus, less area. These findings are verified in high-level and SPICE simulations.

In the end, despite the appealing theoretical benefits of the proposed TRNG noise source, the hardware validation revealed unmodeled noise components, leading to inconclusive results. Consequently, no TRNG implementation based on the designed noise source was made. This highlights the challenges of translating theoretical advantages into successful hardware implementations.

Quantum computing promises revolutionary advancements in computational power by leveraging quantum mechanical phenomena such as superposition and entanglement. Diamond color centers have emerged as promising candidates for quantum information processing due to their long coherence times and scalability. Photonic integrated circuits (PICs), represent a mature technology that facilitates on-chip quantum operations in a compact and scalable manner. In quantum applications, PICs play a crucial role in routing and manipulating quantum information.

The transition to the "More than Moore era," following the plateauing of Moore's law, has highlighted the importance of MEMS (Micro-Electro-Mechanical Systems) technology for continued advancements in electronics. Integrating MEMS with PICs and quantum applications, due to its high performance and mass production capabilities, offers a promising avenue for large-scale device integration and multi-qubit systems.

Designing photonic devices for integration with diamond color-center qubits presents several challenges. Primarily, designing photonic devices for the visible spectrum involves challenges related to device feature sizes approaching the limits of fabrication resolution. Additional challenges include ensuring scalability in quantum computing and compatibility with complementary metal-oxide semiconductor (CMOS) electronics. This requires devices that operate with low power consumption, low actuation voltage, and minimal crosstalk, necessitating significant optimization of MEMS components. Furthermore, integrating MEMS devices demands careful consideration of the mechanical properties of the materials and the designed structures.

This project discusses the design, fabrication, and characterization of a photonic directional coupler for use in beamsplitter and optical MEMS switch configurations in the visible spectrum. The photonic beamsplitter is essential for the controlled manipulation of quantum states, crucial for executing quantum algorithms. The optical MEMS switch provides dynamic control over optical pathways, leveraging the advantages of photonics and MEMS technology. The goal of this project is to optimize the directional coupler design for footprint, and fabrication accuracy, and to propose a directional coupler-based optical MEMS switch design that features low actuation voltage and high extinction ratio. Additionally, this project aims to establish the process recipes for fabricating the designed directional couplers and MEMS components, with particular attention to the physical resolution of small feature sizes, and to evaluate the extent to which the designed performance is achieved. By addressing these topics, the project aims to contribute to the large-scale integration of diamond color center qubits for quantum computing applications.

The importance of cybersecurity is ever more increasing. And with that, the importance of anti-tamper technologies. Physical anti-tamper technologies have existed for a while, but passive (battery-less) approaches are lacking. Some solutions exists ([1], [2] and [3]). But are sparse, complex, expensive and only cover a small portion of the device. The subject of this research is that of Glitter Physical Unclonable Function (PUF). A passive physical anti-tamper technology that protects the whole device, and is technology independent. It works as follows:

The secure component (a Printable Circuit Board (PCB)) is placed in an empty box. A camera and Light Emitting Diode (LED)s are added to the center of the PCB. Then a mixture of glitter and transparent resin is poured into the device (including the camera and lights). The resin hardens and the box is closed (being light tight). Enrolment: A picture is taken with the camera inside the box with the LEDs turned on. The light bounces throughout all the glitters. This picture is used to encrypt the critical data on the PCB. When a tamper has occurred (by pruning the enclosure) the glitters are destroyed or irreversibly moved. Thus the picture taken afterwards is different.
Authentication: Another picture is made. If the picture is within a certain threshold (set in enrolment), being the maximum allowed colour distance for each pixel to the reference picture. Then the picture can be used to decrypt the data. Otherwise, access to the data is lost.

For encryption and error correction several algorithms have been researched and tested. Especially the Error Correcting Code (ECC) used in biometrics are interesting, since they have the same criteria as glitter PUF (using real word data as a key); input data not always being the same. For the protoype Fuzzy Commitment is implemented, being the baseline for biometric encryption. A prototype of the glitter PUF has been made using a Raspberry Pi (RPi) camera and a 3D printed case. This prototype is used to evaluate certain characteristics such as how it behaves in time, temperature difference, ageing and what picture settings are most optimal. These
characterizations are important to know how the device behaves when in operation. As they must deviate from the results gathered when an actual tamper has been taken place.

The ageing and temperature tests show that the sytem is susceptible to temperature cycles, but when the same temperature as the enrolment is reached the difference is lessened. Furthermore, the system seems to stabilize and not increase in error after about 23 cycles. After doing so many cycles it can be calculated which (sub)pixels are the most stable. Choosing only the most stable (sub)pixels for enrolment/authentication will reduce the error introduced by temperature and ageing. Drilling shows a linear increase in (sub)pixel distance from the reference. The drill displays hotspots, whereas the temperature tests (mainly) show noise in the red channel. So an algorithm that considers these differences must be implemented. An implementation using binning for error correction, fuzzy commitment, segmenting the picture in small blocks, using Adaptive Equalization; grey-scaling, and taking only 20% of the most stable (sub)pixels, results in 5% of the original picture data while still containing enough information to reliably detect drilling’s.

Nanomechanical resonators made of two-dimensional (2D) materials are the subject of intensive research due to their remarkable properties, allowing them to operate at high frequencies with high sensitivity. However, dissipation losses and manufacturing issues have prevented them from reaching their full potential. This thesis aims to overcome these challenges by dry-transferring 2D materials onto a MEMS and clamping them using electron beam-induced deposition. By in-plane straining the membranes using MEMS, the tensile energy is increased, thereby diluting intrinsic losses. This approach increased the Q-factor of 2D material resonators by 91% and allowed measuring forces down to sub-piconewtons, outperforming commercially available silicon-based force sensors.

Passivating contacts in the front-rear contacted c-Si solar cells enhances the device performance by quenching the contact recombination and enabling sufficient carrier transport. Tunneling oxide passi- vating contact (TOPCon) which consists of an interfacial oxide and a poly-SiO𝑥 layer is one of the most promising contact techniques in passivating both surfaces of the silicon wafer. However, the full area poly-SiO𝑥 layer is absorptive when it is applied at the front side which has become an efficiency limiting factor. In this project, an advanced local poly-SiO𝑥 passivating contact architecture is proposed and presented. The local poly-SiO𝑥 passivating contacts, so-called “poly-SiO𝑥 finger”, is deposited through a hard mask at predefined locations which will be only placed underneath the metal contacts. The formation of poly-SiO𝑥 finger and its application in the solar cells are discussed.

First, a silicon wafer hard mask is fabricated by a lithography process followed by a KOH wet chemical etch-back process. Specified openings down to 38.7 𝜇m are established which isolate sections of the substrate for the poly-SiO𝑥 finger formation. P+ doped a-SiO𝑥 :H is deposited using PECVD with SiO𝑥 p+ diffused emitter commercial Cz wafers through the hard mask. By investigating the influence of deposition parameters during the PECVD, specifically the power and pressure, decent uniformity of the finger deposition is achieved. An optimized deposition condition of the doped a-SiO𝑥 :H is established for the poly-SiO𝑥 finger formation: an RF power source at 15 Watt, a chamber pressure of 1.5 mbar, and a substrate temperature of 180 °C. A narrow poly-SiO𝑥 finger with a width of 40.0 𝜇m has been demonstrated.

Second, the passivation properties of the symmetrical samples are examined by varying the poly-SiO𝑥 and Al2O3 thickness for the hole carrier selective contacts. A full area p+ TOPCon and Al2O3 symmetric samples were coated on the textured diffused p+ surface with an n-type c-Si substrate to investigate the process parameters on the passivation properties. The optimal 𝑖𝑉𝑜𝑐 of p+ TOPCon samples is 662 𝑚𝑉 and a corresponding 𝐽0 of 156 𝑓 𝐴 𝑐𝑚2 which is obtained with a poly-SiO𝑥 thickness of 50 nm when annealed at 850 °C. The optimal thickness for the Al2O3 passivation layer is achieved by depositing a 20 nm thick layer followed by FGA, with an 𝑖𝑉𝑜𝑐 of 692 𝑚𝑉 and a 𝐽0 of 22.4 𝑓 𝐴/𝑐𝑚2.

Finally, a process flowchart has been created to fabricate c-Si solar cells with the local p+ TOPCon on the front p+ diffused emitter and a full area n+ TOPCon on the rear side. A localized polished area is made by a poly-etch process for the alignment between the substrate and the pattern in the lithography mask. Using the ascertained parameters during the optimization, NAOS-SiO𝑥 combining with 50 nm-thick doped p+ a-SiO𝑥 :H fingers are applied on the p+ diffused surface and 100 nm-thick n+a-SiO𝑥 :H on the rear side. A annealing step is performed for the crystallization. A 20 nm-thick Al2O3 followed by a 75 nm SiN𝑥 layer are deposited on the front side and 100 nm SiN𝑥 layer is applied on the rear side. Lithography, wet chemical etch-back together with Al/Ag(front/rear) evaporation are utilized for solar cells metallization. The fabricated c-Si solar cells with poly-SiO𝑥 fingers has a champion efficiency with an efficiency of 7.91 %, with a 𝑖𝑉𝑜𝑐 of 562 𝑚𝑉, 𝑖𝑛𝑡 𝐽𝑠𝑐 of 34.7 𝑚𝐴 𝑐𝑚2 and fill factor of 40.5 %. The limited performance originates from the poor passivation in the poly-SiO𝑥 local contact area and severe 𝑖𝑉𝑜𝑐 drop after the metallization process. For further improvement, good performing c-Si solar cells by minimizing the recombination in the poly-SiO𝑥 local fingers contacts area and optimizing metallization steps are expected to be fabricated .

Boron-doped diamond (BDD) is a popular material for electrodes and it exhibits metal-like conductivity when a sufficient quantity of boron atoms is incorporated in the diamond lattice. BDD has distinct advantages over alternative electrode materials. It has diamond’s chemical stability and biocompatibility in conjunction with excellent electrochemical characteristics including large potential window and low background current. Thus, BDD has great potential as an electrode material in electrochemical sensors for the detection of pharmaceutical compounds.

Of particular interest is the monitoring of the antidepressants venlafaxine (VF) and desvenlafaxine (DVF). These pharmaceuticals are prescribed to those suffering from major depressive disorder, generalized anxiety disorder, panic disorder and/or social anxiety disorder. However, they can have adverse effects on the health and behaviour of aquatic life, and harmful quantities have already been detected in nature. Monitoring of DVF and VF in a patient’s blood and urine is required to ensure correct dosage levels, which in turn could mitigate environmental pollution. An electrochemical sensor with BDD electrodes would be well-suited for this application.

In this research, two distinct BDD electrode materials were used for the electrochemical detection of VF and DVF. For initial experimentation, a robust and well-established free-standing BDD electrode type was utilized in a voltammetric study. Optimized detection conditions were achieved on hydrogen-terminated BDD for DVF and oxygen-terminated BDD for VF in a 0.1 M H2SO4 solution (pH 0.6), yielding limits of detection (LOD) of 0.31 µM and 0.17 µM and limits of quantification (LOQ) of 0.94 µM and 0.57 µM for VF and DVF, respectively. The scan rate study demonstrated that the oxidation reactions for both compounds are diffusion controlled. VF and DVF have excellent repeatability in the presence of several interfering compounds, such as inorganic ions, sucrose, glucose, and dopamine. To assess the suitability of the detection method, electroanalysis of VF and DVF in synthetic human serum, synthetic urine, and river water was conducted. Besides, a commercially available BDD electrode chip was employed for VF and DVF detection under optimized conditions. The measurement results of the different BDD electrodes were compared; in particular, when the less robust commercial electrode chip was used, larger values of LOD (1.9 µM and 8.0 µM) and LOQ (5.8 µM and 24.1 µM) were reached for VF and DVF, respectively. The fabrication of analogue BDD-based electrochemical sensors by utilizing direct inkjet printing of diamond nanoparticles on silicon substrates was evaluated in parallel. Various electrode designs were successfully printed, however subsequent chemical vapor deposition of thin-film BDD did not satisfy the required electrode quality. Notwithstanding, the use of a BDD electrode allows for the creation of a modification-free and promising practical method for VF and DVF detection.

Silicon heterojunction (SHJ) solar cells are one of the most promising PV technologies nowadays due to high photoconversion efficiencies and low manufacturing costs. However, standard front/back-contacted (FBC) solar cells feature a front metal grid that brings shading to the front side of the devices, which limits the conversion efficiency of solar cells. One solution is to move metal contacts fully to the back by introducing interdigitated-back-contacted (IBC) architecture. In 2018, IBC-SHJ solar cells achieved a photoconversion efficiency of 26.7% holding a record for single-junction c-Si cells. However, the standard fabrication process of IBC solar cells comes with increased complexity and manufacturing costs. The focus of this research is on developing and optimizing a simple and industry-appealing fabrication process for high-efficiency IBC-SHJ solar cells.

The first part of the project investigates the simple processing of IBC-SHJ solar cells featuring tunneling recombination junction (TRJ). The first tunneling IBC devices are fabricated successfully. However, shunting is observed from the J-V curves of fabricated devices, which can be related to the internal shunting of tunneling IBC architecture and high lateral conductivity of p-type nc-Si:H-based blanket layer. Hence, alternative contact stacks are designed for application in the previously developed flowchart with the aim to minimize the lateral conductivity of the blanket layer and keep the fabrication process simple.

The proposed hole collection contact stack is firstly implemented in the front junction (FJ) FBC solar cells. The FJ FBC devices reach Voc of 704 mV and FF of 79.29% . Rear junction (RJ) FBC solar cells are fabricated featuring a novel electron collection contact stack that is developed within this thesis. Voc of 715 mV and FF of 82.24% are obtained in RJ devices. The results of RJ FBC solar cells with a newly developed contact stack show excellent results in terms of FF, making it a promising candidate for further application in IBC devices. The introduction of the optimized device design enabled the successful fabrication of IBC solar cells with the simple process developed for tunneling IBC devices while ensuring no shunting occurs. Fabricated devices represent a proof-of-concept of the novel configuration, providing a promising starting point for future development.

Treatment of diseases, illnesses or disorders are always sought without any undesired side-effects and complications. Neurological disorders, such as Epilepsy and Parkinson’s, are currently treated using pharmaceuticals. However, drugs have a low specificity and lose their effectiveness after several years. In addition, prolonged drug usage often leaves patients with many side-effects and complications. Development in neuroscience indicate the treatment of such neurological disorders via neuro-stimulation. Currently, research in understanding the mechanisms behind neuronal stimulation is carried out by research institutes all around the globe. There are three modes for neuronal stimulation, electrical, optical and lastly the use of ultrasonic waves. As optogenetics provides a more specific technique in neuronal stimulation and electrical recording can provide high spatial resolution data, it is sought to combine this two modes.
This work reports the development of a monolithically fabricated active implant, with optogenetic compatibility using transfer-free graphene electrodes. To achieve this desired goal, a microfabrication process is developed, which is reproducible and scalable with modern day microfabrication technology. In order to be compatible with optogenetics, graphene electrodes are used, as these are transparent and allow for neuronal stimulation using light. The graphene electrodes are grown on a pre-defined molybdenum catalyst, allowing for a transfer-free chemical vapor depostion (CVD) of graphene. Microelectrode-arrays (MEAs) are developed, using graphene electrodes, that include different sized electrodes and different amount of electrodes. The amount being constrained by the available space on the cortex of a mouse.
The aim of this work was to be able to control or read out these MEAs using electronics developed alongside the electrodes. As graphene is grown at a temperature above the melting point of aluminium, conventional CMOS technology can not be used in combination with graphene electrodes. The process developed, did not include any materials which would be damaged during the graphene growth. The metal gate is replaced by a polysilicon gate and the metal interconnects connecting the active devices and the MEAs are defined after the growth of graphene. Resulting in an active implant which is monolithically fabricated in combination with a transfer-free graphene process.
Monolithically fabricating an active graphene based implant, comes with complications. Delamination of the passivisation layer occurred whilst trying to open contact openings to and from the active devices. This was resolved using a more appropriate chemical etchant.
A fully monolithically fabricated active graphene-based implant was obtained. Electrical measurements showed that the active devices did not behave as expected. Revisiting simulations, it was established that there was leakage of dopants from the gate to the channel. This results in the NMOS devices to be always on and the PMOS devices to have a higher threshold voltage.
However, this particular wafer, had many high temperature steps after the doping of the polysilicon. Reduction of these high temperature steps result in less doping getting into the channel. Alternatively, a thicker gate oxide can be used, to serve as a more robust barrier. A last proposed solution is the reduction of the doping concentration and doping energy of the polysilicon, which would result in less dopant being near the gate oxide interface and thus less dopant leaking into the channel.
There are wafers included in this work with less high temperature steps. However, due to time limitation it was not possible to finish production of these wafer in order to confirm it experimentally. Nevertheless, it is believed that with minor adjustments, this research project is a viable foundation for active graphene based implants and structures.

Many semiconductor sensors, particularly MEMS sensors such as inertial, temperature, pressure, and resonance sensors need a vacuum environment for optimal performance and sensitivity in addition to the improvement in their long-term reliability. With the rise of heterogeneous integration with the MEMS and ICs being integrated together, process compatibility becomes a very big issue. Cu is a desirable bonding and sealing material for low-temperature vacuum packaging of next-generation microsystems, as it is compatible with modern CMOS circuits and 3-D IC fabrication. Cu thermocompression bonding has been reported to achieve vacuum sealing at low temperatures, but these approaches need extremely flat and clean Cu surfaces or additional capping layers, and the overall bonding areas are still rather large.
To mitigate this, the use of copper nanoparticles as the sealing material has been proposed. In this study, the first successful demonstration of die and multi-die level hermetic sealing has been demonstrated using Copper nanoparticle paste as the sealing material for sealing ring widths as small as 8$\mu$ at a minimum temperature and pressure levels of 300$^\circ$C and 10 MPa respectively with average encapsulated pressure of 54.18 mbar. Moreover, the leak rate evaluation was conducted which revealed no discernable leakage over a period of 48 days. Finally, the bond shear test and a subsequent failure analysis revealed high densification of the Copper nanoparticles at the bond interface.

Atrial fibrillation (AF) is the most common type of cardiac arrhythmia occurring in around 0.5% of the world population. AF is characterized by the rapid and irregular beating of the atrial chambers of the heart, which can cause lead to strokes and other heart-failures. To prevent these consequences the early detection of AF is paramount. Using photoplethysmography (PPG) heart activity can be measured from which the inter-beat-interval (IBI), the time between heart beats, can be estimated. Using data collected by a PPG sensor the aim is to classify the heart activity as either AF or Normal Sinus Rhythm in real time using machine learning and collect the outcomes for further analysis by medical professionals. For this a classification method is suggested which is able to be implemented on an ARM based processor. Using a Support Vector Machine and 10 features derived from the IBI's and the PPG signal this algorithm achieves the following accuracy metrics: balanced accuracy = 0.853, sensitivity = 0.850, specificity = 0.856 and Matthews Correlation Coefficient (MCC) = 0.643. Compared to similar studies these results are substandard and should be improved.

Crystalline silicon (c-Si) interdigitated back contacted (IBC) solar cell with poly-Si passivating contacts is one of the most promising approaches to achieve high conversion efficiency solar cells. The fabrication of IBC silicon-based solar cells provided by poly-Si passivating contacts is investigated in this thesis. The passivating poly-Si contacts structure used in this work is based on an ultra-thin layer of t-SiOX with optimized poly-Si thicknesses of 250 nm and the implantation parameters of Phosphorous and Boron doping with 6e15 and 5e15 ions/cm2 respectively, at a fixed implantation energy of 20 keV. The influence of the post-implantation annealing conditions is discussed with experimental results, obtained on symmetrical test structures with thermal SiOx/doped poly-Si on each side. The bestobtained passivation result for n+ -poly-Si contact was 728 mV at annealing conditions of 1050°C for 1 minute, while for the p+ poly-Si contact at the same annealing conditions 699 mV is obtained. To enhance the passivation, PECVD deposited SiNX capping layer and annealing in forming gas as hydrogenation processes are carried out. Then, FBC solar cells are fabricated to evaluate the electrical performances, in terms of passivation and carrier transport, of the poly-Si contacts structures, which are prepared with different annealing conditions, in terms of temperature and time. The results obtained from the FBC cells show that increasing the annealing temperature leads to an increase in the passivation thus the VOC. The best-obtained VOC was 706mV for the wafer annealed at 1050°C for 1 minute. To enhance the optical properties of the IBC cells, the surface is textured and the influence of doping dose on passivation of the front surface field (FSF) is evaluated. Four different passivation stack layers SiNX, AlOX/SiNX, a-Si/SiNX, and double SiNy /SiNX are evaluated for FSF implanted with dose of 1e14 ions/cm2. The best-obtained passivation result is from FSF sample passivated with a-Si/SiNX. It shows excellent passivation property with iVOC of 714 mV and a J0 of 7.5 fA/cm2. while the other stacks show lower passivation of iVOC 708 mV for the AlOX/SiNX sample and iVoc=686 mV for the SiNy /SiNX sample. The influence of FGA on the FSF passivation quality is also evaluated. The results show that the sample passivated with a-Si/SiNX experienced a sharp decrease of 35 mV in the iVOC after FGA due to the low thermal stability of the a-Si:H. On the other hand, other FSF samples with passivation stacks of SiNX, AlOX/SiNX, and SiNX /SiNX show a positive influence upon the FGA on their passivation quality as a result of the extra hydrogen diffusion during the FGA which saturates more defects on the c-Si surface. The implantation of the optimized thermal SiOx/ doped poly-Si structure and FSF with a-Si/SiNX passivating layer into the IBC solar cells leads to high-efficiency IBC solar cells. The record cell has a conversion efficiency of 21.04% and 22.15% after the post metallization annealing, VOC of 681 mV, and FF of 78,9 with Jsc of 37.5 mA/cm2

As CMOS scaling approaches the atomic feature size limit which results in a high power density and current leakage, low reliability and increased time and production cost, the need for new materials and devices is increasing. One of the promising materials to replace silicon based devices is graphene nano-ribbons (GNRs) due to its remarkable electronic properties. Theoretical models suggest that 30nm GNR structures can mimic the behaviour of basic Boolean logic gates such as inverter, buffer, or and nor gates while reducing 30x times the propagation delay and using 3000x less gate active area compared to the equivalent CMOS realization. The main goal of this thesis is to fabricate GNR devices that can be ultimately used as building blocks for Boolean logic gates, analyse the limitations of achieving sub-50nm patterns and study the edge termination of the formed GNR patterns. GNR patterns are explored using a simulation model, which can be used for complementary Boolean logic gates. The designed graphene patterns are simulated using tight binding model to calculate the electronic band structure and construct a Hamiltonian matrix. This is followed by calculation of the electronic states and Fermi energies. Non equilibrium Green function (NEGF) models the electrons and holes distribution trough the GNR pattern and the rate at which the charge carriers are transmitted from the source to the drain when they propagate through the device. The result from the NEGF function is used to calculate the charge density using 3D POISSON from which the current through the graphene surface is determined. Finally, with known gate voltages and current, the conductance is found for four different structures in 10 nm and 30 nm technology. By changing the way the structures are connected as pull-up and pull-down network, the behaviour of inverter, buffer, or, and nor gates are obtained. The patterns from the simulation model with 30 nm feature size are used to create a design for devices to be fabricated. In addition, the design includes devices with minimal dimensions from 50 nm to 200 nm, squares, hexagons and pentagons with different dimensions starting from 1 um up to 10 um. For this project, graphene grown by chemical vapour deposition (CVD) was transferred to silicon dioxide samples on which the design of the structures is fabricated. The fabrication process consist of five steps. First, the samples are spin coated with polymethyl-methacrylate (PMMA). Second, electron beam lithography (EBL) is used to pattern the structures, by exposing parts of the resist. Next, the exposed areas are developed in order to remove the resist with introduced damage from the exposure. This is followed by etching the exposed parts of the graphene using oxygen plasma or hydrogen plasma. Finally, the remaining resist is cleaned with acetone. Characterisation of the patterns is performed using Raman spectroscopy, scanning electron microscopy (SEM) and atomic force microscopy (AFM). From the Raman measurements it was found that the edge termination is most likely random and defects are introduced to the lattice of the graphene patterns with left contaminants from the polymer. The achieved minimal feature size of the devices is 50 nm, which was confirmed using AFM and SEM. In addition to the morphological characterisation of the samples, electrical measurements are performed and from the transport characteristics, the electron and hole mobilities of mono layer graphene are derived.

Resistive RAM, or RRAM, is one of the emerging non-volatile memory (NVM) technologies, which could be used in the near future to fill the gap in the memory hierarchy between dynamic RAM (DRAM) and Flash, or even completely replace Flash. RRAM operates faster than Flash, but is still non-volatile, which enables it to be used in a dense 3D NVM array. It is also a suitable candidate for computation-in-memory, neuromorphic computing and reconfigurable computing. However, the show stopping problem of RRAM is that it suffers from unique defects, which is the reason why RRAM is still not widely commercially adopted. These defects differ from those that appear in CMOS technology, due to the arbitrary nature of the forming process. They can not be detected by conventional tests and cause defective devices to go unnoticed. Therefore, new tests need to be developed that properly include the physics of a defective device in a RRAM model. Device-aware testing (DAT) is the state-of-the-art solution to this problem. By accounting for the unique physics of an RRAM device, DAT is able to detect unique RRAM defects. However, DAT bases its results on relatively compact electrical models, which do not account for randomness present in e.g. the forming of the filament and local temperature fluctuations. Meanwhile, many low-level physical models exist already that can model this randomness and provide accurate insights into the physical specifics of RRAM. These models do, however, hardly ever analyze the effects of defects. The contribution of this work is to expand and improve one of the state-of-the-art physical models to analyse manufacturing defects on a low, near atomic-level scale. For the first time, the characteristics of a defect can be described in the physical shape of the defect, rather than only the electrical consequences of a black box device. This enables deep level analysis and characterization of defects, the results of which improves DAT to detect even more unique defects. The model is applied to four types of RRAM-related defects: oxygen vacancy density fluctuation, oxide thickness variation, electrode roughness, and contamination by impurities. The effect of the defects on the conductivity of the device are observed and explained, and their unique non-linear behavior is confirmed by simulation. Dynamic defects are not yet included, but the model does provide an extensive static characterization of unique RRAM defects, providing insights into their behavior and improving the quality of DAT. Finally, a discussion is presented which criticizes the reproducability of the referenced defect-free model, but also shows the potential of this work's model to be improved.

In the advanced semiconductor industry, modern electronic devices are expected to realize complex functions with minimized size, which requires an increase in the density of on-chip interconnects. To meet this demand, the dimension of interconnects is reduced and it requires the narrowing of metal interconnects to carry the increasing current density. With such a developing trend, electromigration is one of the significant reliability challenges for electronic devices. Although lots of works focus on the formulation and simulation for electromigration, they are not complete and consistent with experimental results. Recently, A fully-coupled and self-consistent electromigration theory was developed by Cui et al, but new and extensive experimental data and analysis are needed to further validate their theoretical results.
This research work focuses on the experimental study on electromigration (EM), and the aim is to investigate the different effects on EM. The Blech structure was proposed as our experimental structure. The fabrication of Blech structure is conducted at the EKL cleanroom, and main structures with various dimensions are fabricated by employing sputtering technique for deposition and lithography for defining patterns. The measurement is carried out by accelerated tests with high current stress and at elevated temperature. Experimental results are characterized and analyzed by different tools, such as Keyence 3D laser profilometer and scanning electron microscope
With the current density of 1×1010퐴/푚2 and temperature of 250 ℃, the result shows that the critical length under certain conditions is 10 μm, and longer stripes have larger drift lengths and a shorter time to form voids in electromigration. Furthermore, it is found that with elevated temperature, the drift length increases and the electromigration lifetime decreases. In addition, the covered SiN passivation layer only for the annealed Al stripes suppresses electromigration and this is because the annealing process improves the coalescence of grain in Al film, reducing the defects at the grain boundary and finally forming a denser microstructure. The influence of the atmosphere on electromigration indicates that the additional oxide on Al interconnects increases that actual current stress and results in a short electromigration lifetime. In general, present experimental results were consistent with existing results in the literature, but several problems are still unsolved, which will be part of our future work.

The COVID-19 pandemic caused a shortage of Personal Protective Equipment for Healthcare personnel. This project aims to aid in this shortage by extending the lifetime of the filter material used in a mask. This is done in the form of an SPPE, a Smart Personal Protective Equipment. This face mask has two smart filter heads that are modular and contain UVC LEDs to disinfect the filter, a control system to control the LED's radiative power and an on-board power management system. The latter is the focus of this thesis.

The implementation of an on-board power management system for a smart personal protection face mask was designed in three stages: (1) researching existing theory about battery management, (2) implementing and verifying a system design in Simulink and (3) making a PCB design and selecting off-the-shelf components. The goal of this thesis is to make a complete design of a functional battery management system, that supplies required power to the rest of the system, ensuring safe battery operation and aiming to maximize battery life. In this, the design has succeeded as almost all requirements are met. The result is a PCB design that can be made and combined with two other subgroups to create a Smart Personal Protection face mask. The main findings were a different and possibly new approach to estimating the State of Charge of a battery and designing a Battery management system for low power applications in a small form factor as opposed to battery management systems for electrical vehicles, which are common today.

This work presents a low-noise amplifier (LNA) for ultrasound imaging with built-in continuous time-gain compensation (TGC), which compensates for the time-dependent attenuation of the received echo signal and thus significantly reduces its dynamic range (DR). The proposed design combines the LNA and TGC functions in a single variable-gain current-to-current amplifier. Compared to conventional ultrasound front-ends, which implement the TGC function after an LNA that needs to handle the full DR of the echo signal, this approach can highly reduce the power consumption and the size. Compared to earlier programmable-gain LNAs with discrete gain steps, the continuous gain control avoids switching transients that may lead to imaging artefacts. The TGC function is realized by a novel feedback network consisting of a double differential pair that feeds a fraction of the output current back to the input. This fraction can be changed continuously using a control voltage that is applied to the gates of the differential pairs, to realize a gain range from -20 dB to +20 dB. To achieve an approximately constant closed-loop bandwidth in the presence of the changing feedback factor, a loop amplifier has been implemented whose gain is changed along with the feedback factor by dynamically changing its bias currents. This loop amplifier employs a current-reuse architecture to achieve high power-efficiency. In addition, a variable bias current source has been designed to appropriately bias the TGC feedback network. By employing a similar double differential pair topology as in the feedback network, this current source provides the required low noise at the highest gain setting and high current at the lowest gain setting within the available headroom. The LNA with built-in TGC function has been realized in 180nm CMOS technology. It has been optimized to interface with a 7.5 MHz CMUT transducer. Simulation results show that it achieves a 3dB bandwidth higher than 40 MHz across the full gain range. At the highest gain setting, its input current noise is 0.96 pA/sqrt(Hz). This leads to an input dynamic range of 93 dB, which is compressed into an output dynamic range of 53 dB by means of the 40 dB variable gain. The amplifier consumes 10.8 mW from a 1.8V supply, and occupies an estimated 302 x 320 um2 die area.

On-chip spectrometers, such as DESHIMA and SuperSpec, require transmission lines with very low loss of tanδ < 10^-4 to achieve sufficient system efficiency. Transmission lines with higher loss would introduce too much signal attenuation in the line from antenna to filter and in the filters themselves. Data regarding the losses of transmission lines at THz frequencies and sub-K temperatures is severely lacking. In this report an on-chip Fabry-Pérot resonator concept is demonstrated that can be used to measure the losses of a transmission line with high sensitivity at high frequencies. To create the in-line Fabry-Pérot resonator, a transmission line of certain length is coupled to a THz source via a twin-slot lens antenna on one side and to an Al-NbTiN hybrid MKID on the other side. The goal of this work is to measure the losses of microstrip lines at frequencies > 300 GHz, at a temperature of about 250 mK, with dielectric dominated loss in the range of 10^-3 > tanδ > 10^-5. There are several experimental challenges for measuring tanδ. The first challenge is the limited frequency resolution of the source, due to which resolving low tanδ can become impossible. Secondly it was experimentally found that there is stray light coupled to the detector which causes a spurious response with a level of −30dB with respect to the peak (unity) transmission of the Fabry-Pérot resonator. Taking these experimental challenges into account results in a Fabry-Pérot resonator design where the length, the mode number, and the coupler quality factor Q_c of the resonator are optimized. Furthermore multiple resonators on a single chip are used, each coupled to a separate antenna and detector, with different Q_c values. This design method is applicable for different dielectric materials and different transmission line configurations. Using this method a chip was designed and fabricated for a microstrip line based Fabry-Pérot resonator fabricated from sputter deposited superconducting NbTiN metal and a PECVD deposited a-Si layer. Using this chip a tanδ ≈ 10^-4 @ 350 GHz was measured, which represents the lowest loss values of a microstrip line at frequencies > 10 GHz ever measured.