As quantum systems increase in complexity, accurately reconstructing quantum states becomes a fundamental challenge. Quantum state tomography (QST) provides a framework for reconstructing quantum states from experimental measurements. However, the computational resources required for QST scale exponentially with the number of qubits as the Hilbert space dimension grows as N = 2^n, where n is the number of qubits and N the resulting probability amplitudes. This exponential growth renders traditional approaches computationally prohibitive for systems beyond a few qubits. Recent advancements in machine learning have introduced neural network-based approaches to QST, such as variational autoencoders (VAEs) and restricted Boltzmann machines (RBM). These methods leverage the representational power of neural networks to approximate high-dimensional quantum states efficiently. However, the energy-intensive nature of artificial neural networks (ANNs) poses scalability concerns, particularly as quantum systems grow larger. Recent advancements in machine learning have introduced neural network-based approaches to QST, such as VAE and RBM. These methods leverage the representational power of neural networks to approximate high-dimensional quantum states efficiently. Neuromorphic computing offers a biologically inspired paradigm for addressing the challenges of QST. This event-driven architecture allows for asynchronous computation with significantly lower energy consumption compared to traditional neural networks. The RBM trained on the BrainScales-2 (BS2) Neuromorphic platform exhibited low fidelity because of the limited neuron availability and the 6-bit weights on the BS2. The novelty of this thesis is the idea that a variational autoencoder can be split on the level encoder and decoder and let the encoder outside of the BS2 use a bigger model. This results in the question of how a fully spiking variational autoencoder (FSVAE) can be effectively implemented on neuromorphic hardware to achieve high fidelity and scalability for quantum state tomography. Firstly, a quantum state is prepared using unitary operators, and S (also known as Shots) times are measured to create a dataset to interconnect the Qubit information with the FSVAE. This dataset consists of a set of one hot encoded vectors that represent the quantum state and are scaled by 4N. Lastly, the FSVAE consists of an encoder that is built on the CPU and a decoder that is built on the BS2. The results came from implementing these methods by training the FSVAE (encoder-decoder) on a CPU-CPU configuration and a CPU-BS2 configuration. Two experiments were conducted to compare the performance of BS2 in the configuration mentioned earlier. The CPU-CPU configuration could be trained for 3 to 7, and the CPU-BS2 configuration could be trained for 2 to 5 qubits in the Greenberger–Horne–Zeilinger (GHZ) state. The two configurations are compared, and the MSE loss did not converge on the CPU- BS2 configuration as low as the CPU-CPU configuration. The discrepancy results from BS2 having 6-bit weights and the CPU 32-bit weights. Despite this difference, the fidelity of reconstructing by the FSVAE of 4 qubits is improved by around 20% compared to the RBM architecture.

The rapid advancement of neural network applications, including multilayer perceptrons (MLP) and deep convolutional neural networks (CNN), has revolutionized domains such as image recognition, speech processing, and classification. However, the increasing depth and complexity of neural network workloads impose significant computational and energy demands. Conventional hardware, such as CPUs and GPUs, faces growing challenges in meeting these demands due to the "memory wall" problem and the diminishing benefits of Moore’s law and Dennard scaling. These issues are particularly pronounced in edge devices where power and energy efficiency are critical.

To address these limitations, computing-in-memory (CIM) architectures, particularly memristor-based crossbar arrays, have emerged as promising solutions. CIM reduces data movement by performing computations directly within memory, significantly improving energy efficiency and performance. Memristor crossbars excel in analog matrix-vector multiplication (MVM), a fundamental operation in neural networks, making them an ideal candidate for accelerating neural network workloads.

This thesis proposes an end-to-end compilation framework that automates the translation and optimization of neural networks for CIM architectures. The framework supports converting high-level MLP models represented in PyTorch into low-level instructions optimized for crossbar-based spatial CIM architectures. Comprehensive experiments explore the impact of various quantization schemes and design space parameters, revealing trade-offs between performance, energy efficiency, and resource utilization. The results demonstrate the framework's potential to support diverse neuromorphic systems and facilitate the efficient deployment of neural networks on CIM architectures.

With the prosperity of the Internet of Things (IoT) and artificial intelligence (AI), more and more edge devices have been deployed to enable intelligent applications. However, due to the limited energy budget and computation resources, it is challenging to deploy deep neural networks on edge devices directly. The energy consumption of the memory transfer between the processor and memory is a significant part of the total energy consumption, which is the bottleneck of traditional von Neumann architecture. Computation in memory (CIM) is a promising architecture that can significantly reduce this energy consumption by minimizing the data movement between the processor and memory. By utilizing the novel non-volatile memory (NVM) technology, the computation can be performed in the memory in analog domain, which can reduce the energy consumption and latency of the computation. However, the existing periphery of CIM architecture, which is responsible for converting the result of the computation in memory to the digital domain, is not energy-efficient and has a large area overhead. In this thesis, we propose a novel AI-based periphery for CIM architecture to address these issues. The proposed periphery is based on the neural network, which can be trained to convert the crossbar output to the digital domain with high accuracy. Multiple inputs, up to four crossbar columns with different significant levels, can be processed simultaneously and output the shift-and-add result in the digital domain in one shot, without the need for multiplexers or post-processing circuits. Moreover, a new coding scheme called natural Palindromic Coding (NPC), is proposed to encode the output of the neural network, which aims to mitigate the spectral bias of the neural network, where high-frequency components, like the least significant bit (LSB), are underrepresented. Benchmarking results show that the proposed AI-based periphery, with 4 parallel 4-bit inputs and 8-bit output, can achieve 81.16% accuracy or 99.5% accuracy with 1 unit step tolerance. Under the MNIST dataset, the proposed NPC can achieve an accuracy of 96.80%, compared with 97.07% of software inference. In addition, the proposed periphery can achieve 31.77× energy saving and 9× area saving compared with the state-of-the-art neural-network-based periphery, or up to 1.65× energy saving and 2.70× area saving compared with the state-of-the-art SAR-ADC-based periphery.

Neuromorphic architectures are energy efficient architectures for executing spiking neural networks. Current open-source neuromorphic hardware projects are either experimentation platforms (RANC, ODIN) or neural network accelerators (Open-Spike, SNE), there are no direct processing platforms that support AI and ML applications. Seneca-Lite is an open-source RISC-V based multicore neuromorphic platform. The goal of Seneca-Lite is to enable new possibilities for AI and ML applications and foster more collaboration in this field. The platform is intended for research and academic purposes and furthering the field of neuromorphic computing.

The Seneca-Lite platform utilizes the Ibex core, a highly parameterizable open-source 32 bit RISC-V processor. Each core in the Seneca-Lite platform contains a Network On Chip (NoC) router, local memories, network message FIFOs and interconnects. The multi-core platform is designed to facilitate messaging between cores via the NoC. The NoC used in Seneca-Lite is the same as the NoC used in RANC (Reconfigurable Architecture for Neuromorphic Computing). The number of cores in the system is parameterized and can be controlled by the user depending on their need. Since the platform is open-source, many of the internal parameters (Ibex parameters, FIFO parameters etc) can be tweaked by the user as per their target application.

The completed neuromorphic platform is benchmarked for various state-of-the-art applications and compared to other neuromorphic platforms.

One-third of patients suffering from chronic epilepsy, which is caused by abnormal brain activity, is drug-resistant. Animal models are widely used to study the mechanisms leading to epilepsy so better drug treatments can be developed for this disease. In such studies, epileptiform activity, assessed by LFP recordings, can be used as a marker for the development and chronification of disease. However, the analysis of LFP recordings is typically done manually, which is time-consuming, subject to observer bias, error-prone, and lacks consistency and efficiency. Therefore, we present a work which developed a new, automated detection and classification method for epileptiform activity, which was tested in the intrahippocampal kainic acid (IHKA) mouse model, a model of human temporal lobe epilepsy. Our method relies on a spike detector using an improved version of the nonlinear energy operator (NEO) in combination with automatic NEO thresholding (ANT). The detected spikes form the basis of epileptiform event detection and classification. The proposed method is implemented in Python as an automated and time-efficient algorithm that can be used in preclinical studies. Epileptiform event detection accuracy was 93.1% and classification accuracy 95.8%. Moreover, the time for analysis of LFP recordings was reduced by 98.8% compared to manual analysis. Additionally, to demonstrate the potential of the algorithm for application in Brain-Machine Interfaces (BMI), we performed a real-time implementation using both an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA). The FPGA demonstrated the feasibility of real-time implementation, and the ASIC resulted in an area and power efficient chip using the Taiwan semiconductor manufacturing company (TSMC) 45nm library that constitutes a post-layout area of 9114 µm2 and a power usage of 6.11 µW.

Deep Neural Networks (DNNs) have revolutionized numerous computational fields, from image and speech recognition to autonomous driving and natural language processing. Yet, the substantial computational and energy requirements of DNNs, particularly Convolutional Neural Networks (CNNs), pose significant obstacles to their deployment on resource-constrained edge devices. This thesis presents SPARO, a novel Scalable Sparsity-Aware Event-Driven Architecture designed to overcome these challenges by effectively exploiting sparsity in both neural network weights and activations.
SPARO’s architecture is founded upon a unique event-driven dataflow that harnesses the inherent sparsity of CNNs, thereby reducing computational burden and energy consumption. This dataflow is strategically divided into two distinct phases: the Update Phase and the Fire Phase. During the Update Phase, all computations essential for incoming events are executed, while the Fire Phase is dedicated to applying non-linear activation functions and pooling operations to the output feature maps (OFM). This meticulously designed phased approach streamlines data handling, eliminates redundant computations, and significantly boosts overall processing efficiency.
A cornerstone of SPARO’s innovation is its dynamic weight reuse mechanism, which intelligently maximizes the reuse of weights across multiple events. This significantly reduces the number of weight fetches needed, thereby improving arithmetic intensity. Furthermore, SPARO leverages advanced sparse data representation techniques to minimize memory usage and further enhance computational efficiency.
The efficacy of SPARO is demonstrated through comprehensive evaluations using both synthetic benchmarks and real-world CNN applications, such as gesture recognition and object detection. In the same form-factor, SPARO achieves an impressive 8.5x speedup compared to the baseline Seneca system, delivering real-time performance while consuming only 14% of the energy for the TinyYolo vision task.

Memory advances have not kept up with computing demands. Emerging device technology Resistive RAM (RRAM) addresses this by enabling computation-in-memory. However, RRAM suffers from read disturb, limiting viability. While earlier work has had some success in reducing read disturb by switching the read current direction (a bipolar read scheme), the RRAM device eventually degraded. In this work, a reinforcing bipolar read scheme is introduced, which aims to prevent read disturb by reinforcing both HRS and LRS, away from the undefined state. From device-level simulation, this reinforcing behaviour is predicted for V = 0.5, 0.4 and 0.3 V with a fixed switching ratio between time under positive and negative read voltage polarity rsw i tch = 2.5, 2.5 and 2.75, respectively. At V = 0.2 V and V = 0.1 V, it is predicted that no reinforcement scheme exists. The bipolar read scheme found for V = 0.5 V was evaluated in circuit simulation with a sense amplifier. however the HRS and LRS reinforcing behaviour found at device-level could not be replicated. From unipolar read results at circuit level, it was determined no switching ratio exists that reinforces both the HRS and LRS state boundaries as chosen here at RHRS,min = 12.8kΩ and RLRS,max = 4.4kΩ for V = 0.5 V. However, a 5.1x reduction in resistance drift compared to conventional unipolar read was still obtained.

Conventional computing systems involve physically separated storing and processing units. To perform the processing, data is shuttled from the storing unit to the processing unit followed by the actual processing, and the processed data is shuttled back into the storing unit. Unfortunately, this data shuffling contributes significantly to the overall latency and energy consumption of the system. Computation-in-memory (CIM) offers a promising alternative that can process the data within the storing unit, thereby, alleviating the need for data shuffling. This can potentially lead to high energy efficiency and high throughput computation. In addition, emerging non-volatile memristors provide an excellent storing element that can inherently perform the computation in CIM while also retaining the data value.
Memristor-based CIM has been vastly explored to perform certain data-intensive computational tasks for numerous applications related to artificial intelligence (AI), Big Data, and data encryption while realizing high-performing, low-power micro-architectural solutions. This thesis first identifies the existing key challenges related to emerging memory technology and CIM memory array, and the circuit design of periphery logic to achieve low-power and high-performing CIM units. Thereafter, it presents several micro-architectural solutions to build CIM accelerators that can perform logic and arithmetic operations in an efficient manner.

Identifying the challenges of memristor-based CIM: The thesis briefly summarizes the key aspects of a memristor-based CIM architecture that can perform certain logic and arithmetic operations. First, the key components of a typical CIM architecture are presented, highlighting the design considerations to build these components. An account of computational accuracy and efficiency share of each of these components is presented supported by a comprehensive literature survey while highlighting the underlying concepts of each component. This is followed by identifying the key challenges in achieving stringent efficiency metrics required by the targeted applications while dealing with non-idealities. Finally, the limitations of the state-of-the-art solutions that target these challenges are highlighted, thus, providing the motivation to develop outperforming solutions that are presented in the thesis.

Developing micro-architectural solutions for efficient CIM-based logic accelerators: This part of the thesis presents several logic accelerators that can perform (N)OR, (N)AND, and XOR operations in a fast and energy-efficient manner. \textbf{FIVE} different solutions target different aspects of performing CIM-based logic, whereby, scaling the number of operands per cycle and the memory size, and expanding to different types of operations that can be supported while addressing the non-idealities. State-of-the-art solutions are comprehensively outperformed by our proposed solutions in terms of energy efficiency, performance, and the maximum number of operands that can be accurately performed in a single cycle.

Developing micro-architectural solutions for efficient CIM-based arithmetic accelerators: This part of the thesis presents several compact arithmetic accelerators that can perform multiply-and-accumulate (MAC) operations with low energy consumption. \textbf{THREE} different analog-to-digital converter (ADC) topologies are presented with two of them demonstrated with a chip prototype. Optimizing the memory structure is also explored to ensure accurate generation of analog output in the CIM memory array and to optimize the A/D conversion. A comparison of the proposed solutions with the state-of-the-art is presented, highlighting the promise of the developed micro-architectures.@en

Artificial intelligence (AI) is rapidly becoming an integral part of many real-world products and services. This is mainly facilitated by the extensive computing resources provided by the cloud infrastructure. However, cloud-based AI processing suffers from drawbacks like high latency, huge network costs, data privacy/security concerns, and service disruptions due to internet outage. Edge computing for AI (edge-AI) addresses these problems by combining data sources with on-board AI processing hardware. Such hardware must be energy efficient to achieve prolonged operation, given the limited energy resources on edge devices. Moreover, it should be compact in size to facilitate seamless system integration and enhanced portability. Conventional hardware cannot meet these requirements due to data transfer bottleneck in von Neumann architecture and limitations of conventional memory technologies.
Computation-in-memory (CIM) overcomes these challenges by in-situ data processing using emerging memory technologies called memristors. Thus, CIM can facilitate energy efficient and compact edge-AI hardware design. Healthcare domain stands out as a prime target for CIM-based edge-AI hardware, due to two main reasons. Firstly, it holds significant real-world importance due to its direct impact on human well-being. Secondly, the increasing adoption of AI in healthcare can significantly benefit from efficient hardware for data processing. CIM-based edge hardware can greatly enhance the effectiveness of AI-based healthcare through rapid, reliable, and secure processing of medical data at its source. Hence, design of CIM-based edge-AI hardware for healthcare applications presents a promising research direction.

The process of designing CIM-based edge-AI hardware for healthcare can be expressed as a stack of six abstraction layers: application, algorithm, optimization, mapping, micro-architecture and circuits, and device. These abstraction layers can be further grouped into two distinct design phases. The first phase is application-dependent, covering the first three abstraction layers (application, algorithm and optimization). It involves creating a customized neural network model for the given healthcare application. The challenge in this phase is to achieve strong algorithmic performance, while incorporating features to exploit the full potential of CIM hardware. Conversely, the second phase is application-independent and comprises of the remaining abstraction layers (mapping, micro-architecture and circuits, and device). It solely focuses on translating the model computations into CIM hardware operations. However, the non-ideal characteristics of memristor devices introduce computational errors in hardware operations. This undermines the advantages of CIM as energy-efficient computations are of no use if they are incorrect. Hence, mitigating memristor non-idealities becomes the primary challenge in this phase. Moreover, it is important to integrate the customized model and non-ideality mitigation strategies into a comprehensive hardware solution and realize it through prototyping. This gives rise to the following three research topics: 1) healthcare AI models for CIM-based edge hardware, 2) dealing with memristor non-idealities, and 3) CIM edge-AI prototyping for healthcare.

We adopt a cross-layer approach in this thesis to address these research topics, covering all six layers of the CIM abstraction stack. We begin by creating neural network models for two healthcare applications: cardiac arrhythmia classification and diabetic retinopathy screening. Our contributions in this application-dependent design phase span across the first three abstraction layers (application, algorithm and optimization). At the application layer, we introduce new features in the model tailored to the specific healthcare application. This enhances its real-world impact by addressing the unique medical needs more effectively. Moving to the algorithm layer, we customize the computational flow within the model to exploit the characteristics of the healthcare data. This improves design performance in key aspects like accuracy and energy efficiency. Moreover, we strategically refine the model computations to further maximize post-deployment benefits on CIM hardware. At the optimization layer, we employ techniques like resampling, quantization and pruning to optimize hardware resource requirements, without compromising the model's algorithmic performance.

After creating the neural network models, we proceed to the application-independent design phase. Focusing on RRAM-based memristor devices, we first identify three key non-idealities that significantly impact inference accuracy on CIM hardware. We then devise mitigation strategies against these non-idealities, encompassing the remaining abstraction layers (mapping, micro-architecture and circuits, and device). At mapping layer, we propose a hardware-aware training methodology to combat the conductance variation non-ideality. Moving to the micro-architecture level, we present two mitigation strategies. The first addresses non-zero Gmin error non-ideality through a novel approach to CIM micro-architecture design. The second introduces an adaptive micro-architecture that adjusts its sensing conditions to counteract the effects of read-disturb non-ideality. At the device level, these strategies indirectly contribute by circumventing the necessity for extensive device engineering, ensuring accurate inference even in the presence of non-idealities. Building upon this foundation of model development and non-ideality mitigation, we integrate the optimal ECG classification model with the proposed mitigation strategies to create a CIM edge-AI prototype. Thus, our contributions pave the way towards a future with enhanced effectiveness and efficiency of AI-powered healthcare.@en

Cardiovascular diseases (CVDs) are the top cause of death worldwide, and their diagnosis can be quickly and painlessly achieved through Electrocardiogram (ECG). The diagnosis of electrocardiogram has gradually evolved from manual diagnosis by doctors to one that can be realized using Artificial Intelligence (AI). Early AI still required manual extraction of features for ECG classification, but later Deep Neural Network (DNN) could automatically extract features during the learning process. With this technology, people can monitor heart movements in real-time through wearable devices. If there are any abnormalities, they can seek medical treatment in time to prevent death from sudden severe heart disease. However, for the wearable device, the energy consumption per classification by the traditional AI is so high that a limited battery cannot work for a long time.

To address this issue, this thesis adopts Spiking Neural Network (SNN) to do classification and implement the inference on the hardware. Compared with traditional Artificial Neural Network (ANN), SNN is highly energy efficient. According to the needs of SNN and its event-driven characteristics, the multi-threshold-based encoding scheme is proposed, which encodes the heartbeat into 54 spikes on average with less information loss. The SNN model is trained by ANN-SNN conversion with an accuracy of 97.42\%. After RTL coding, synthesis, and back-end implementation, the chip with encoding and inference functions achieves an energy consumption of only 57.88 nJ per heartbeat classification.

Ultra-low power Edge AI hardware is in increasing demand due to the battery-limited energy budget of typical Edge devices such as smartphones, wearables, and IoT sensor systems. For this purpose, this Thesis introduces an ultra-low power event-driven SRAM-based Compute In-Memory (CIM) accelerator optimized for inference of Binary Spiking Neural Networks (B-SNNs). In this Thesis, a custom-designed 3nm SRAM cell is developed, with up to four read ports to improve inference performance and one transposable read/write port for efficient on-chip learning functionality. The event-based nature of SNNs is exploited to minimize the computation and memory cost. The design benefits from technology scaling of fully digital design by synthesizing the accelerator in the imec 3nm FinFET technology node. The proposed accelerator's performance is evaluated by running MNIST inference at 97.6% accuracy, achieving an impressive throughput of 44M inferences/s at 607 pJ/inference (3.2 fJ per synaptic operation) while running at 29 mW. The results demonstrate that the proposed accelerator provides an energy-efficient and high-performance solution for inference of Binary SNNs, opening up new possibilities for Edge AI applications.

The advent of Artificial Intelligence (AI) and Internet-of-things (IoT) has led to a significant demand for edge computing and enabling Neural Network Implementation on edge devices. However, due to large MAC operations involved in the implementation of Neural networks, the traditional digital hardware based on the von-Neumann architecture is not well suited for an edge device. Computation-in-Memory (CIM) is an attractive alternative in mitigat- ing the challenges involved with traditional hardware by directly processing the data within the memory. It utilizes emerging memory devices such as Resistive Random Access Memory (RRAM) to perform in-place computations in the analogue domain, thereby, eliminating the bottlenecks associated with the constant movement of data in the von-Neumann architecture. However, the standard implementation of CIM comes with several challenges, with the pri- mary being high power consumption, which debate its implementation on an edge device in accelerating Neural network computation. Thus, this work proposes a novel CIM crossbar that has the potential to alleviate the challenges associated with the standard CIM cross- bar. Subsequently, an ultra-low power micro-architecture design is proposed, based on the novel CIM crossbar, that can accelerate Binary Neural Networks (BNN) and Spiking Neural Networks (SNN) with high power efficiency. The benchmark results obtained over the imple- mentation of custom-developed BNN and SNN, trained over the MNIST dataset, indicate a power reduction of 13x and 26x respectively for the proposed micro-architecture, compared to its standard CIM crossbar counterpart. In addition, the proposed micro-architecture exhibits energy savings of around 4-5x over both BNN and SNN, making it a promising alternative for accelerating neural network computation over edge devices.

The ever-increasing energy demands of traditional computing platforms (CPU, GPU) for large-scale deployment of Artificial Intelligence (AI) has spawned an exploration for better alternatives to existing von-Neumann compute architectures. Computation In-Memory (CIM) using emerging memory technologies such as Resistive Random Access Memory (RRAM) provide an energy-efficient and scalable alternative for Deep Neural Networks (DNN) applications. However, the benefits of CIM frameworks come at the cost of low DNN accuracy due to non-idealities in RRAM devices. In this thesis we address the conductance variation non-ideality in RRAM devices at an architectural level. We present two mapping schemes to improve the accuracy of CIM-based DNNs in the presence of RRAM conductance variation. Experimentation conducted with five datasets show that all proposed schemes provide up to 5.4x accuracy improvement over state-of-the-art implementations while inducing a 1.5% area cost and up to 10% energy overhead. Based on accuracy-energy trade-off, the thesis concludes the proposed Complementary Conductance Matrix (CCM) is the best candidate to improve inference accuracy of neural networks on CIM hardware using RRAM. It reports an accuracy improvement up to 5x with 1.52% area overhead and 9% energy overhead.

Cardiac arrhythmia characterized by irregular heartbeats is a prevalent problem among people suffering from cardiovascular diseases (CVD). Abnormalities in the heartbeats manifested in the electrocardiogram (ECG) signal are traditionally analysed by expert cardiologists or semi-automated computer aided techniques, which can be time consuming. Recent deep neural network (DNN) methods have paved the way for fully-automated timely classification. However, low accuracy and high energy consumption are few of the common problems with the existing DNN methods. In this work, a complete solution based on hierarchical three stage DNN architecture is proposed using Resistive Random Access Memory (RRAM) based Computation in-memory (CIM) architecture. The proposed scheme using Fully Connected Network (FCN), Long Short Term Memory Network (LSTM), assisted with dimensionality reduction and online personalized partial training enables a high accuracy and energy-efficient ECG arrhythmia classification solution. Experimental study conducted with MIT-BIH arrhythmia database show that the proposed scheme achieves an accuracy of 98.73%, F1 score of 97.6%, and consumes 442.25 uJ of energy. Compared to state-of-the-art, energy improvement of up to 2.83x is achieved, with a reasonable area overhead.

Epilepsy is a system-wide phenomenon which manifests physically across the body in various forms such as rapid muscle tone, sweating, elevated heart rate and synchronized neuron firing. Many of these aspects appear ahead of an epileptic incident. If combined together, these aspects are tell-tale signs of an imminent ictal event. Because of these observations, a wireless medical body area network (MBAN) has been proposed, which implements multimodal-data integration and closed-loop seizure suppression. The design and implementation of the MBAN introduces several challenges, such as data collection, seizure prediction and suppression, secure pairing and communication and the design of a user friendly interface. This thesis will focus on the design and implementation of a secure bus architecture that connects multiple processing cores, a sensor and an actuator within an MBAN node. The interconnect will provide communication between the masters and slaves via an AMBA AHB-Lite protocol. Furthermore, a memory protection unit (MPU) will deny accesses from unauthorized peripherals. Additionally, the prototype will provide a secure communication protocol for updating the MPU. Finally, the prototype will be able to communicate wirelessly with a smartphone. The deliverable will be a proof-of-concept implementation on an FGPA, demonstrating the previously described functionalities. Nevertheless, the design choices will be made with the application in mind.

Epilepsy is a severe neurological disorder that affects every aspect of a patient’s life. Unfortunately, there is no complete cure for everyone on the market yet. However, a lot of work has been done on seizure prevention. The entire project details the proof of concept implementation of a secure and reliable MBAN (Medical Body Area Network) used for seizure prevention. The principal objective of the MBAN system is to set up and maintain secure connections between the nodes of the MBAN system and store and analyze the received data in the cloud. Therefore, a suitable gateway is needed, which is created in this work. The gateway concerns a mobile application constructed with the Flutter SDK. The main ability of the applicaton is to communicate with the implantable medical device, which in the demonstration is the node the gateway is connected to using BLE. The application is designed for Android and iOS and is connected to the AWS cloud service in which the data is stored and analyzed with a simple function that checks whether the received heart rate is above a certain threshold. This function can be easily replaced by a more extensive function. In addition, the application displays user health metrics such as the heart rate, connection state, and it can update the firmware of the implantable medical device. The security measures taken in this project concern setting up the BLE connection with an OOB (Out Of Band) channel for key sharing, after which the key is used to encrypt the data streams. Additionally, the data in the cloud is encrypted.

Diabetic Retinopathy (DR) is one of the leading causes of permanent vision loss. Its current prevalence is around 45 millions across the globe and is projected to 70 million by 2045. Most of the people with this disease condition belong to remote and low income settings. We can reduce this incidence, if quality medical care is accessible in remote areas. With the current advancements in imaging technologies, fundus examination can be carried out on a handheld device. We need to improve such devices to deliver high quality services through auto detecting DR based on convolutional neural networks(CNNs) in an offline setting. Addressing these challenges, we aim to develop an integrated solution which delivers high compute at ultra-low power consumption. Firstly, we have created 3 datasets of different sizes merging multiple public datasets to create a vigilant model training process. This is to make the CNN model robust to real-world noise. CNNs trained on smaller datasets have shown a 15% accuracy drop on evaluation datasets where as CNNs trained on large datasets showed consistent performance. Secondly, we have proposed a new binary labelling scheme using multi-class output to maximize the utility of its softmax probabilities. We have achieved 90.26% accuracy on evaluation dataset with the new scheme. These high performing models along with compression techniques are implemented on resistive random access memory (RRAM) based computational in memory (CIM) architecture. These implementations resulted in atleast 200x improvement in energy consumption for inferring on one image when compared to CPU, GPU and mTPU (google coral dev board). Similarly, latency improvements 28x,130x and 2000x compared GPU,CPU and mTPU are registered. Model quantization with 4-bit precision for weights have preserved the original accuracy and showed 4x improvements in energy consumption on RRAM implementation.