As spin-based quantum processors grow in size and complexity, maintaining high fidelities and minimizing crosstalk will be essential for the successful implementation of quantum algorithms and error-correction protocols. In particular, recent experiments have highlighted pernicious transient qubit frequency shifts associated with microwave qubit driving. Work-Arounds for small devices, including prepulsing with an off-resonant microwave burst to bring a device to a steady state, wait times prior to measurement, and qubit-specific calibrations all bode ill for device scalability. Here, we make substantial progress in understanding and overcoming this effect. We report a surprising nonmonotonic relation between mixing chamber temperature and spin Larmor frequency which is consistent with observed frequency shifts induced by microwave and baseband control signals. We find that purposefully operating the device at 200 mK greatly suppresses the adverse heating effect while not compromising qubit coherence or single-qubit fidelity benchmarks. Furthermore, systematic non-Markovian crosstalk is greatly reduced. Our results provide a straightforward means of improving the quality of multispin control while simplifying calibration procedures for future spin-based quantum processors.

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A strained Ge quantum well, grown on a SiGe/Si virtual substrate and hosting two electrostatically defined hole spin qubits, is nondestructively investigated by synchrotron-based scanning X-ray diffraction microscopy to determine all its Bravais lattice parameters. This allows rendering the three-dimensional spatial dependence of the six strain tensor components with a lateral resolution of approximately 50 nm. Two different spatial scales governing the strain field fluctuations in proximity of the qubits are observed at <100 nm and >1 μm, respectively. The short-ranged fluctuations have a typical bandwidth of 2 × 10-4 and can be quantitatively linked to the compressive stressing action of the metal electrodes defining the qubits. By finite element mechanical simulations, it is estimated that this strain fluctuation is increased up to 6 × 10-4 at cryogenic temperature. The longer-ranged fluctuations are of the 10-3 order and are associated with misfit dislocations in the plastically relaxed virtual substrate. From this, energy variations of the light and heavy-hole energy maxima of the order of several 100 μeV and 1 meV are calculated for electrodes and dislocations, respectively. These insights over material-related inhomogeneities may feed into further modeling for optimization and design of large-scale quantum processors manufactured using the mainstream Si-based microelectronics technology.

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This magazine is both an introduction into quantum computing and an exploration of its impact on our world. It follows on from our 2019 magazine on the quantum internet. Since 2019, much progress has been made in quantum technologies worldwide. In 2020, for instance, the first European quantum computer came online in Delft. Although this is meant for experiments only, it shows that quantum computing is becoming real. We aim to present you with a basic picture of quantum computing, and sketch applications for which it can be used. The contents are meant to be accessible, but some texts may be more suitable for readers with a basic understanding of quantum technology. Let that not be a reason to stop exploring: the magazine is meant to be browsed, so you can find the articles that help you learn about quantum computers. At TU Delft, we see it as our responsibility to investigate and inform you about the impact of the technologies we develop. Hence, we also explore the potential impact of quantum computing on the world: how the expected wave of applications may ripple through society. This exploration is partly guess-work. Quantum computing is a new technology and no doubt more applications will be discovered. Moreover, while as a university we are good at describing what quantum computing is, it will be future users who determine what meaning its applications will have. That is why we also asked the help of experts in and outside of academia when exploring the impact of quantum computing. This magazine is the result of the work by the Quantum Computing Vision Team. Vision teams are composed of TU Delft scientists and engineers from many disciplines, and with vision teams TU Delft participates in public discussions on technologies. We hope this magazine offers you insights of what quantum computing can bring, and invites you to become part of the discussion of how we can make quantum computing meaningful to you and to society. @en

One of the main components used in superconducting quantum chips is the Josephson junction. Currently when fabricating Josephson junctions, the resistance uniformity at wafer-scale is not optimal. It is also known that an annealing process can alter the junction resistance and with it the qubit frequency. However, laser annealing has only shown to be able to increase the junction resistance. An equally effective and minimally invasive technique to decrease junction resistance is necessary to have full control on frequency
targeting. Thermal annealing in a reducing environment is known to result in a global decrease in junction resistance. To get better control on frequency targeting the techniques could be combined. A die containing not-capped Manhattan type Josephson junctions has been annealed using forming gas at 200°C for 2 minutes, based on a non-linear least squares reciprocal function fit to the data an asymptotic lower bound of 467 μSμm^-2 for the change in conductance per unit area has been found. Smaller junctions with an area
of approximately 0.03 μm² undergo a bigger change in conductance per unit area of around 800 μSμm^-2. Annealing at higher temperatures such as 300 and 400°C results in a decrease of the conductance. There is no substantial change in yield of usable SQUIDs when using a rapid thermal annealing process.

A hole bilayer in a strained germanium double quantum well is designed, fabricated, and studied. Magnetotransport characterization of double quantum well field-effect transistors as a function of gate voltage reveals the population of two hole channels with a high combined mobility of (Formula presented.) and a low percolation density of (Formula presented.). The individual population of the channels from the interference patterns of the Landau fan diagram was resolved. At a density of (Formula presented.) the system is in resonance and an anti-crossing of the first two bilayer subbands is observed and a symmetric-antisymmetric gap of (Formula presented.) is estimated, in agreement with Schrödinger-Poisson simulations.

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Spin qubits in silicon have emerged as a promising candidate for a scalable quantum computer due to their small footprint, long coherence times, and their compatibility with advanced semiconductor manufacturing. However, all known spin qubit material hosts come with specific challenges, that limit the performance of quantum information processing. In this thesis we study Si/SiGe heterostructures, comprising a strained silicon (Si) quantum well which is sandwiched between two silicon-germanium (SiGe) barriers. Si/SiGe heterostructures designed to act as solid-state matrix to host spin qubits have three intrinsic material challenges that limit performance: hyperfine interaction, valley splitting, and charge noise. Therefore, to realize a scalable quantum computer in Si/SiGe heterostructures we first quantify the performance limiting parameters and subsequently, we improve them systematically with statistical significance. Acquiring data with statistical significance, however proves challenging for quantum devices in Si/SiGe heterostructures due to complicated and time-consuming fabrication schemes for device manufacturing, and the need of using dilution refrigerators that cool samples down to sub-Kelvin temperatures with only a limited amount of wires for electrical characterization of devices. Therefore, in this thesis we demonstrate fast growth-fabrication-measurement feedback cycles to accelerate our understanding on the materials and devices. We realize such fast feedback cycles by first establishing a unique workflow at TU Delft, allowing 100~mm wafer growth and fabrication. Subsequently in our first experiment, we overcome the wiring bottleneck by presenting a cryogenic multiplexing platform that multiplies DC wires inside of a dilution refrigerator. This cryogenic multiplexer platform uses commercially available CMOS components, is compatible with any dilution refrigerator, and allows us to measure thirteen chips in the same cooldown at a temperature of 50~mK and at magnetic fields of up to 10~T. We confirm these extreme measurement conditions by showing statistically significant quantum transport properties of industrially grown 300~mm $^{ ext{nat}}$Si/SiGe wafers. In the following experimental chapters we then leverage the cryogenic multiplexer to successively tackle the performance limiting parameters of spin qubit processors in Si/SiGe heterostructures. In the second experiment we first analyze valley splitting in two dimensional electron gases and observe that valley splitting increases linearly with the electric field at the quantum Hall edge states of the device at a rate consistent with theoretical predictions. In turn, this observation allows us to evaluate valley splitting on a micron length scale with relatively simple Hall-bar measurements. In the third experiment we show two major improvements in our heterostructures. First, we measure valley splitting in quantum dots with varying quantum well interface sharpness with statistical significance. We then proceed to analyze the atomic composition of the quantum well interfaces in several samples using atom probe tomography and show that Ge atoms are distributed randomly in each atomic layer. Subsequently using the atom probe tomography results as input, we simulate valley splitting and show that valley splitting depends on the atomistic details of the interface and needs to be treated as a statistical distribution. We then propose a strategy to increase valley splitting on average above a chosen threshold by introducing a small concentration of Ge atoms into the quantum well. Second, all electrical measurements in this experiment are performed in isotopically purified $^{28}$Si quantum wells, which reduces the hyperfine interaction and hence increases qubit coherence times. While we do not explicitly discuss this improvement in this chapter, it is a crucial baseline for all following experiments in this thesis and for all qubit experiments using Delft grown $^{28}$Si/SiGe heterostructures. We then move to show wafer-scale improvements of the disorder landscape of Si quantum wells in our fourth experiment. There, we challenge the common approach of growing an epitaxial Si cap on the $^{28}$Si/SiGe heterostructure, by replacing the Si cap with an amorphous Si-rich layer. We compare these two heterostructues by monitoring the statistical performance of mobility, percolation density, maximum electric field before hysteresis, and single particle relaxation time and observe a statistical performance increase of the mean value and the standard deviation. In the fifth experiment we study a heterostructure with a thin quantum well and compare its statistical performance of mobility, percolation density, and charge noise with the performance of the heterostructures from the preceding experiment. Importantly, we find that misfit dislocation arising from strain relaxation are significantly reduced in thin quantum wells as confirmed by geometrical phase analysis of transmission-electron microscope images. In consequence, we observe a statistical performance increase of all key metrics in the novel heterostructure, only possible by our approach of engineering the critical material layers. Finally, we see promising simulated qubit coherence times and qubit error rates when using our charge noise results as simulation input, hinting at a practical advantage of our novel $^{28}$Si/SiGe heterostructures for quantum processors. In the last experimental chapter we demonstrate how our improved $^{28}$Si/SiGe heterostructures have enabled two key experiments in the field of spin-based quantum computing. First, we show that our purified heterostrucures may host high-quality qubits, that in turn serve as a testbed for demonstrating CMOS-based cryogenic control of silicon quantum circuits. Second, we show how our isotopically purified, low-disorder heterostructures host a 6-qubit quantum processor with high-fidelity initialization, high-fidelity gate operation, and high-fidelity readout. We conclude this thesis by highlighting key improvements of our $^{28}$Si/SiGe hetero-structures that have contributed to state-of-the-art spin qubit experiments. However, our heterostructures still require further improvements if we want to achieve error rates around 10$^{-6}$ and scale to large spin qubit arrays with more than a million qubits. Therefore, we discuss additional material changes that could further lower spin qubit error rates and we consider how to assess the uniformity of the material over different length scales, relevant when striving for larger qubit arrays. @en

Quantum computers based on semiconductor quantum dots are proving promising contenders for large scale quantum information processing. In particular, group IV based semiconductor hosts containing an abundance of nuclear spin-zero isotopes have made considerable headway into fulfilling the requirements of a universal quantum computer. Silicon (Si) and germanium (Ge) are two elements that have played important roles in the history of classical computing, and are now poised to do the same in the future of quantum computation. In this thesis, we advance efforts in developing a quantum computer in both Si, using electron spins in Si-metaloxide- semiconductor (SiMOS) hosted quantum dots, and hole spins in planar germanium quantumwells (Ge/SiGe). @en

Atom probes generate three-dimensional atomic-scale tomographies of material volumes corresponding to the size of modern-day solid-state devices. Here, the capabilities of atom probe tomography are evaluated to analyze buried interfaces in semiconductor heterostructures relevant for electronic and quantum devices. Employing brute-force search, the current dominant reconstruction protocol to generate tomographic three-dimensional images from Atom Probe data is advanced to its limits. Using Si/SiGe heterostructure for qubits as a model system, the authors show that it is possible to extract interface properties like roughness and width that agree with transmission electron microscopy observations on the sub-nanometer scale in an automated and highly reproducible manner. The demonstrated approach is a versatile method for atomic-scale characterization of buried interfaces in semiconductor heterostructures.

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High-purity crystalline solid-state materials play an essential role in various technologies for quantum information processing, from qubits based on spins to topological states. New and improved crystalline materials emerge each year and continue to drive new results in experimental quantum science. This article summarizes the opportunities for a selected class of crystalline materials for qubit technologies based on spins and topological states and the challenges associated with their fabrication. We start by describing semiconductor heterostructures for spin qubits in gate-defined quantum dots and benchmark GaAs, Si, and Ge, the three platforms that demonstrated two-qubit logic. We then examine novel topologically nontrivial materials and structures that might be incorporated into superconducting devices to create topological qubits. We review topological insulator thin films and move onto topological crystalline materials, such as PbSnTe, and its integration with Josephson junctions. We discuss advances in novel and specialized fabrication and characterization techniques to enable these. We conclude by identifying the most promising directions where advances in these material systems will enable progress in qubit technology.

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We engineer planar Ge/SiGe heterostructures for low disorder and quiet hole quantum dot operation by positioning the strained Ge channel 55 nm below the semiconductor/dielectric interface. In heterostructure field effect transistors, we measure a percolation density for two-dimensional hole transport of 2.1 × 10 10 cm−2 , indicative of a very low disorder potential landscape experienced by holes in the buried Ge channel. These Ge heterostructures support quiet
operation of hole quantum dots and we measure an average charge noise level of √SE = 0.6 μeV/√Hz at 1 Hz, with the lowest level below our detection limit√SE = 0.2 μeV/√Hz. These results establish planar Ge as a promising platform for scaledtwo-dimensional spin qubit arrays@en

Single-charge pumps are the main candidates for quantum-based standards of the unit ampere because they can generate accurate and quantized electric currents. In order to approach the metrological requirements in terms of both accuracy and speed of operation, in the past decade there has been a focus on semiconductor-based devices. The use of a variety of semiconductor materials enables the universality of charge pump devices to be tested, a highly desirable demonstration for metrology, with GaAs and Si pumps at the forefront of these tests. Here, we show that pumping can be achieved in a yet unexplored semiconductor, i.e. germanium. We realise a single-hole pump with a tunable-barrier quantum dot electrostatically defined at a Ge/SiGe heterostructure interface. We observe quantized current plateaux by driving the system with a single sinusoidal drive up to a frequency of 100 MHz. The operation of the prototype was affected by accidental formation of multiple dots, probably due to disorder potential, and random charge fluctuations. We suggest straightforward refinements of the fabrication process to improve pump characteristics in future experiments 2021 The Author(s). Published by IOP Publishing Ltd.

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This dissertation describes a set of experiments with the goal of creating a super-conductor-semiconductor hybrid circuit quantum electrodynamics architecture with single electron spins. Single spins in silicon quantum dots have emerged as attractive qubits for quantum computation. However, how to scale up spin qubit systems remains an open question. The hybrid architecture considered here could provide a route to realizing large networks of quantum dot–based spin qubit registers. The first experiment in this thesis is aimed at achieving strong coupling between a single electron spin and a single microwave photon. The electron is trapped in a gate-defined double quantum dot in a Si/SiGe heterostructure and the photon is stored in an on-chip superconducting high-impedance NbTiN cavity. The photon is coupled directly to the electron charge, and indirectly to the electron spin, mediated through a synthetic spin-orbit field. We observe a vacuum Rabi splitting that depends on the spin-charge hybridization. The ratio of spin-photon coupling strength to decoherence rates of the spin and cavity combined is larger than unity, confirming the strong coupling regime has been reached. In addition, we find an optimal degree of spin-charge hybridization for which this ratio is maximized. The demonstration of strong spin-photon coupling not only opens a new range of physics experiments, but fulfills also a crucial requirement for coupling spin qubits at a distance via a cavity. The second experiment is focused on spin readout with the on-chip cavity. Instead of the direct dispersive readout of a single spin, we use the cavity to detect whether the electron is allowed to tunnel between the two dots or not. We benchmark the charge sensitivity and bandwidth of the detector and find that rapid detection of the electron charge with high SNR is possible. In the two-electron regime, electron tunneling is contingent on the total spin state (Pauli spin blockade). This spin-to-charge conversion scheme enables single-shot detection of singlet states with high-fidelity. The demonstration of single-shot spin readout with a cavity is an essential step towards readout in dense spin qubit arrays, such as the crossbar network, where it is not possible to integrate electrometers and accompanying reservoirs adjacent to the qubit dots. In the third experiment, we develop on-chip microwave filters to suppress microwave photon leakage from the cavity through the gate electrodes that are necessary to form quantum dots. We introduce a new cavity design that is compatible with long-distance connectivity between spins, but is also more susceptible to microwave leakage. We test and compare two low-pass filter variations in terms of performance, footprint and integrability. They use the same nanowire inductor, but different implementations of the capacitor: one with a planar interdigitated capacitor and one novel design with an overlapping thin-film capacitor. We find that both approaches are effective against microwave leakage. However, the large footprint of the interdigitated capacitor makes this solution inconvenient as the number of gate lines increases. The thin-film capacitor, with its much smaller footprint, is better suited for our devices. The final part of this dissertation contains concluding remarks and possible future directions are proposed. @en

Topological superconductivity can be engineered in semiconductors with strong spin-orbit interaction coupled to a superconductor. Experimental advances in this field have often been triggered by the development of new hybrid material systems. Among these, two-dimensional electron gases (2DEGs) are of particular interest due to their inherent design flexibility and scalability. Here, we discuss results on a 2D platform based on a ternary 2DEG (InSbAs) coupled to in situ grown aluminum. The spin-orbit coupling in these 2DEGs can be tuned with the As concentration, reaching values up to 400 meV Å, thus exceeding typical values measured in its binary constituents. In addition to a large Landé g-factor of ∼55 (comparable to that of InSb), we show that the clean superconductor-semiconductor interface leads to a hard induced superconducting gap. Using this new platform, we demonstrate the basic operation of phase-controllable Josephson junctions, superconducting islands, and quasi-1D systems, prototypical device geometries used to study Majorana zero modes.

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We investigate hole spin relaxation in the single- and multihole regime in a 2 × 2 germanium quantum dot array. We find spin relaxation times T1 as high as 32 and 1.2 ms for quantum dots with single- and five-hole occupations, respectively, setting benchmarks for spin relaxation times for hole quantum dots. Furthermore, we investigate qubit addressability and electric field sensitivity by measuring resonance frequency dependence of each qubit on gate voltages. We can tune the resonance frequency over a large range for both single and multihole qubits, while simultaneously finding that the resonance frequencies are only weakly dependent on neighboring gates. In particular, the five-hole qubit resonance frequency is more than 20 times as sensitive to its corresponding plunger gate. Excellent individual qubit tunability and long spin relaxation times make holes in germanium promising for addressable and high-fidelity spin qubits in dense two-dimensional quantum dot arrays for large-scale quantum information.

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Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantum-computing system can be achieved, thus promising scalability to the large number of qubits required in a practical application. This work presents a cryo-CMOS microwave signal generator for frequency-multiplexed control of 4\times 32 qubits (32 qubits per RF output). A digitally intensive architecture offering full programmability of phase, amplitude, and frequency of the output microwave pulses and a wideband RF front end operating from 2 to 20 GHz allow targeting both spin qubits and transmons. The controller comprises a qubit-phase-tracking direct digital synthesis (DDS) back end for coherent qubit control and a single-sideband (SSB) RF front end optimized for minimum leakage between the qubit channels. Fabricated in Intel 22-nm FinFET technology, it achieves a 48-dB SNR and 45-dB spurious-free dynamic range (SFDR) in a 1-GHz data bandwidth when operating at 3 K, thus enabling high-fidelity qubit control. By exploiting the on-chip 4096-instruction memory, the capability to translate quantum algorithms to microwave signals has been demonstrated by coherently controlling a spin qubit at both 14 and 18 GHz.

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Buried-channel semiconductor heterostructures are an archetype material platform for the fabrication of gated semiconductor quantum devices. Sharp confinement potential is obtained by positioning the channel near the surface; however, nearby surface states degrade the electrical properties of the starting material. Here, a 2D hole gas of high mobility (5 × 10⁵ cm² V⁻¹ s⁻¹) is demonstrated in a very shallow strained germanium (Ge) channel, which is located only 22 nm below the surface. The top-gate of a dopant-less field effect transistor controls the channel carrier density confined in an undoped Ge/SiGe heterostructure with reduced background contamination, sharp interfaces, and high uniformity. The high mobility leads to mean free paths ≈ 6 µm, setting new benchmarks for holes in shallow field effect transistors. The high mobility, along with a percolation density of 1.2 × 10¹¹cm⁻², light effective mass (0.09m_e), and high effective g-factor (up to 9.2) highlight the potential of undoped Ge/SiGe as a low-disorder material platform for hybrid quantum technologies.

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In the version of this Letter originally published, the second, third and fourth exponential terms in equation (3) were incorrect; the corrected equation is shown below. (Formula presented.). The correct equation was used for data analysis. The online versions have been amended.@en

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

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