Cavity-enhanced diamond color center qubits can be initialized, manipulated, entangled, and read individually with high fidelity, which makes them ideal for large-scale, modular quantum computers, quantum networks, and distributed quantum sensing systems. However, diamond’s unique material properties pose significant challenges in manufacturing nanophotonic devices, leading to fabrication-induced structural imperfections and inaccuracies in defect implantation, which hinder reproducibility, degrade optical properties and compromise the spatial coupling of color centers to small mode-volume cavities. A cavity design tolerant to fabrication imperfections─such as surface roughness, sidewall slant, and nonoptimal emitter positioning─can improve coupling efficiency while simplifying fabrication. To address this challenge, a deep learning-based optimization methodology is developed to enhance the fabrication error tolerance of nanophotonic devices. Convolutional neural networks (CNNs) are applied to promising designs, such as L2 and fishbone nanobeam cavities, predicting Q-factors at least one-million times faster than traditional finite-difference time-domain (FDTD) simulations, enabling efficient optimization of complex, high-dimensional parameter spaces. The CNNs achieve prediction errors below 3.99% and correlation coefficients up to 0.988. Optimized structures demonstrate a 52% reduction in Q-factor degradation, achieving quality factors of 5 × 104 under real-world conditions and a 2-fold expansion in field distribution, enabling efficient coupling of nonoptimally positioned emitters. Compared to previous deep-learning optimization methods, this approach achieves twice the Q-factor performance in the presence of fabrication errors, significantly enhancing device robustness. Hence, this methodology enables scalable, high-yield manufacturing of robust nanophotonic devices, including the cavity-enhanced diamond quantum systems developed in this study.@en

Low-loss visible-light photonic circuits are crucial for high-performance photonic quantum processors. By using aluminum oxide (Al₂O₃) for its low visible-light absorption, we achieved waveguides exhibiting an exceptionally low propagation loss (1.39 dB/cm for the transverse electric mode) at red-light wavelengths. Directional coupler beam splitters fabricated using this platform exhibited good controllability of the optical splitting ratios. Furthermore, we fabricated a half beam splitter, which is an essential component of entangled photon generation in quantum optics. These results represent a significant advance toward developing low-loss photonic circuits, paving the way for improved performance in photonic quantum processors.

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Quantum computation represents a promising frontier in the domain of high-performance computing, blending quantum information theory with practical applications to overcome the limitations of classical computation. This study investigates the challenges of manufacturing high-fidelity and scalable quantum processors. Quantum gate set tomography (QGST) is a critical method for characterizing quantum processors and understanding their operational capabilities and limitations. This paper introduces Ml4Qgst as a novel approach to QGST by integrating machine learning techniques, specifically utilizing a transformer neural network model. Adapting the transformer model for QGST addresses the computational complexity of modeling quantum systems. Advanced training strategies, including data grouping and curriculum learning, are employed to enhance model performance, demonstrating significant congruence with ground-truth values. We benchmark this training pipeline on the constructed learning model, to successfully perform QGST for 2 and 3 gates on single-qubit and two-qubit systems, with over-rotation error and depolarizing noise estimation with comparable accuracy to pyGSTi. This research marks a pioneering step in applying deep neural networks to the complex problem of quantum gate set tomography, showcasing the potential of machine learning to tackle nonlinear tomography challenges in quantum computing.@en

Memristor technology has shown great promise for energy-efficient computing [1] , though it is still facing many challenges [1 , 2]. For instance, the required additional costly electroforming to establish conductive pathways is seen as a significant drawback as it contributes to power and area overheads, and limited device endurance. In this work, we propose a novel forming-free HfO₂ -based ReRAM device with low operating voltages , multi-level capability , and less sensitivity to device-to-device (D2D) and cycle-to-cycle (C2C) variations. The device is fabricated using CMOS-compatible processes, excluding the undesirable complex steps mandatory to manufacture the state-of-the-art forming-free devices [3, 4, 5]. This is accomplished by utilizing the desirable formation energy of Pd-O bonds [6, 7], which creates conducting paths at room temperature while maintaining the analog switching ability of the devices. The proposed ReRAM device holds a great value for dense memories and energy-efficient compute architectures.

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For quantum computing modules using diamond color centers, we propose an integrated structure of a quantum chip with photonic circuits and an interposer with electric circuits. The chip and interposer are connected via gold stud bumps using flip-chip bonding technology. For evaluating the proposed integrated structure, we bonded a test chip of 15 × 15 mm2, corresponding to the area that allows the allocation of color center qubits in the order of 102, with an interposer of 20 × 20 mm2, including test measurement lines. We confirm all connections of 16 lines with two bumps for each line at 10 K. The resistance of the lines with two bumps at 10 K is ~ 3.5O, These resistances are mainly attributed to the gold lines on the interposer, which is confirmed by simulations. The shear strength of the flip-chip bonded structure is 67 g/bump. It is larger than that of previous reports where the chips passed the standard temperature cycle test. Moreover, we integrate the flip-chip bonded structure with a printed circuit board (PCB). We confirm a connection between the connector terminal of the PCB and the test chip at 80 K. It is shown that the integrated structure using gold stud bumps has a potentially highly reliable connection at cryogenic temperature. These results will lead to realizing large-scale diamond spin quantum processors.

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Surface-activated direct bonding of diamond (100) and c-plane sapphire substrates is investigated using Ar atom beam irradiation and high-pressure contact at RT. The success probability of bonding strongly depends on the surface properties, i.e, atomic smoothness for the micron-order area and global flatness for the entire substrate. Structural analysis reveals that transformation from sapphire to Al-rich amorphous layer is key to obtaining stable bonding. The beam irradiation time has optimal conditions for sufficiently strong bonding, and strong bonding with a shear strength of more than 14 MPa is successfully realized. Moreover, by evaluating the photoluminescence of nitrogen-vacancy centers in the diamond substrate, the bonding interface is confirmed to have high transparency in the visible wavelength region. These results indicate that the method used in this work is a promising fabrication platform for quantum modules using diamonds.

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Quantum computer chip based on spin qubits in diamond uses modules that are entangled with on-chip optical links. This enables an increased connectivity and a negligible crosstalk and error-rate when the number of qubits increases onchip. Here, 3D integration is the key enabling technology for a large-scale integration of the diamond spin qubits with photonic and electronic circuits for routing, control and readout of qubits. There are several engineering challenges to integrate the large number of spins in diamond with the on-chip circuits operating at a cryogenic temperature. In this paper we will address challenges, present recent results and discuss future outlook of the integration technology for realization of a scalable quantum computer based on diamond spin qubits.

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Quantum computer chip based on spin qubits in diamond uses modules that are entangled with on-chip optical links. This enables an increased connectivity and a negligible crosstalk and error-rate when the number of qubits increases on-chip. Here, 3D integration is the key enabling technology for a large-scale integration of the diamond spin qubits with photonic circuits and CMOS electronics for routing, control and readout of qubits. Several engineering challenges exist in order to integrate the large number of spins in diamond with the on-chip circuits operating at a cryogenic temperature. We will review trends, address challenges and discuss future outlook of the integration technology for realization of a scalable quantum computer based on diamond spin qubits.

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3D integration has well-developed for traditional CMOS technology operating at room temperature, but few studies have been performed for cryogenic applications such as quantum computers. In this paper, a wafer-to-wafer bonding of superconductive joints based on niobium nitride (NbN) is performed to demonstrate the possibility of 3D integration of superconducting chips. The NbN thin films are deposited by magnetron sputtering. Its high critical temperature (15.2 K) is achieved by optimizing the sputtering recipe in terms of N₂ flow rate and discharge voltage. Wafer-level bumping is bonded by the thermo-compression method. The sheet resistance of the thin film and the contact resistance of the joints are measured by the Greek-cross (4-point Kelvin method) and daisy chain structures at cryogenic temperature, respectively. Direct-bonding wafers with NbN superconductive joints avoid using adhesive layers and the bonding interface could still present superconducting electrical connections in a cryogenic environment above 4 K, which will allow us to use a smaller and high-cooling power cryostat. The contribution of this work could lead to the fabrication of multi-layered superconducting chip that operates beneficially in cryogenic temperature, which is essential in building scalable quantum processors.

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For future integration of a large number of qubits and complementary metal-oxide-semiconductor (CMOS) controllers, higher operation temperature of qubits is strongly desired. In this work, we fabricate p-channel silicon quantum dot (Si QD) devices on silicon-on-insulator for strong confinement of holes and investigate the temperature dependence of Coulomb oscillations and Coulomb diamonds. The physically defined Si QDs show clear Coulomb diamonds at temperatures up to 25 K, much higher than for gate defined QDs. To verify the temperature dependence of Coulomb diamonds, we carry out simulations and find good agreement with the experiment. The results suggest a possibility for realizing quantum computing chips with qubits integrated with CMOS electronics operating at higher temperature in the future.

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Physically defined silicon triple quantum dots (TQDs) are fabricated on a silicon-on-insulator substrate by dry-etching. The fabrication method enables us to realize a simple structure that does not require gates to create quantum dot confinement potentials and is highly advantageous for integration. We observe the few-electron regime and resonant tunneling points in the TQDs by applying voltages to two plunger gates at a temperature of 4.2 K. Moreover, we reproduce the measured charge stability diagram by simulation with an equivalent-circuit model composed of capacitors and resistors. The equivalent-circuit simulation makes it clear that we realize three QDs in series within the nanowire, as planned. This circuit model also elucidates the mechanism of resonant tunneling and identifies a quadruple point of TQDs.

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Solid-state qubits integrated on semiconductor substrates currently require at least one wire from every qubit to the control electronics, leading to a so-called wiring bottleneck for scaling. Demultiplexing via on-chip circuitry offers an effective strategy to overcome this bottleneck. In the case of gate-defined quantum dot arrays, specific static voltages need to be applied to many gates simultaneously to realize electron confinement. When a charge-locking structure is placed between the quantum device and the demultiplexer, the voltage can be maintained locally. In this study, we implement a switched-capacitor circuit for charge-locking and use it to float the plunger gate of a single quantum dot. Parallel plate capacitors, transistors, and quantum dot devices are monolithically fabricated on a Si/SiGe-based substrate to avoid complex off-chip routing. We experimentally study the effects of the capacitor and transistor size on the voltage accuracy of the floating node. Furthermore, we demonstrate that the electrochemical potential of the quantum dot can follow a 100 Hz pulse signal while the dot is partially floating, which is essential for applying this strategy in qubit experiments.

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Photon-counting imaging technology has applications in many fields such as fluorescence lifetime imaging microscopy (FLIM), time-resolved Raman spectroscopy, 3D imaging, and even space communications. The requirement to detect single photons with picosecond temporal resolution makes single-photon avalanche photodiode (SPAD) a popular choice. Advanced biomedical imaging applications such as pill cameras, retinal prosthesis, and implantable biocompatible monitoring sensors require a compact image system, which can be implanted into a living body. To meet these requirements, novel single-photon image sensor solution needs to be developed, in which new substrate post-processing and backside illumination or even dual-side illumination are core technologies, with inherent CMOS compatibility as a prerequisite. This chapter proposed and demonstrated the world’s first flexible CMOS single-photon avalanche diode image sensor, providing a suitable solution for implantable biomedical imaging or monitoring applications, and wherever a curved imaging plane is essential.@en

A novel, simple, low-cost method for the void-free filling of high aspect ratio (HAR) through-silicon-vias (TSVs) is presented. For the first-time pure indium, a type-I superconductor metal, is used to fill HAR vias, 300 to 500 μm in depth and 50 to 100 μm in diameter. The low electrical resistivity achieved without sintering, its reproducibility and straightforward processing steps, and the short time required to fill large arrays of vias at wafer scale - all make this method one of the simplest and quickest options for filling HAR TSVs for MEMS 3D integration. Moreover, the low melting point (∼ 150 °C), malleability and superconductivity at 3.41 K make indium an interesting option in 3D interconnects for connecting quantum devices operating below 4 K.

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Silicon can be printed using liquid silicon ink, which is a mixture of polymerized cyclopentasilane (CPS) and a solvent. Thermal annealing higher than 350oC of this material, however, was necessary, to convert it to solid silicon, which prevented its usage on inexpensive substrates with a limited thermal budget. We review a novel method that forms polycrystalline silicon (poly-Si) patterns directly on paper using the same liquid silicon with doctor-blade coating and local irradiation of excimer-laser with room temperature process. We review also the process and electrical properties of poly-Si TFTs fabricated on the paper. This technique will breakthrough the printed electronics by enabling applications such as fast printed electronics that are inexpensive, fully-recyclable, biodegradable and even edible.@en